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| SH7011 hardware manual ade-602-169 rev. 1.0 12/2/98 hitachi, ltd.
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. i contents section 1 SH7011 overview .......................................................................................... 1 1.1 SH7011 overview............................................................................................................ .. 1 1.1.1 SH7011 features................................................................................................... 1 1.2 block diagram .............................................................................................................. ..... 4 1.3 pin arrangement and pin functions .................................................................................. 5 1.3.1 pin arrangement ................................................................................................... 5 1.3.2 pin functions ........................................................................................................ 6 section 2 cpu ..................................................................................................................... 9 2.1 register configuration ..................................................................................................... .. 9 2.1.1 general registers (rn).......................................................................................... 9 2.1.2 control registers .................................................................................................. 10 2.1.3 system registers................................................................................................... 11 2.1.4 initial values of registers .................................................................................... 11 2.2 data formats............................................................................................................... ....... 12 2.2.1 data format in registers ...................................................................................... 12 2.2.2 data format in memory........................................................................................ 12 2.2.3 immediate data format ........................................................................................ 12 2.3 instruction features....................................................................................................... ..... 13 2.3.1 risc-type instruction set.................................................................................... 13 2.3.2 addressing modes ................................................................................................ 16 2.3.3 instruction format ................................................................................................ 20 2.4 instruction set by classification ........................................................................................ 23 2.5 processing states.......................................................................................................... ...... 36 2.5.1 state transitions.................................................................................................... 36 section 3 power-down state .......................................................................................... 39 3.1 overview................................................................................................................... ......... 39 3.1.1 power-down state ................................................................................................ 39 3.2 sleep mode ................................................................................................................. ....... 40 3.2.1 transition to sleep mode...................................................................................... 40 3.2.2 exit from sleep mode........................................................................................... 40 section 4 clock pulse generator (cpg) ..................................................................... 41 4.1 overview................................................................................................................... ......... 41 4.2 clock source............................................................................................................... ....... 41 4.2.1 crystal resonator connection .............................................................................. 41 4.2.2 external clock input ............................................................................................. 43 4.3 usage notes ................................................................................................................ ....... 43 ii section 5 exception processing ..................................................................................... 45 5.1 overview................................................................................................................... ......... 45 5.1.1 types of exception processing and priority......................................................... 45 5.1.2 exception processing operations ......................................................................... 46 5.1.3 exception processing vector table...................................................................... 47 5.2 resets ..................................................................................................................... ............ 49 5.2.1 reset.................................................................................................................... .. 49 5.2.2 power-on reset .................................................................................................... 49 5.3 address errors............................................................................................................. ....... 50 5.3.1 address error exception processing .................................................................... 50 5.4 interrupts ................................................................................................................. ........... 51 5.4.1 interrupt priority level ......................................................................................... 51 5.4.2 interrupt exception processing ............................................................................. 52 5.5 exceptions triggered by instructions ................................................................................ 52 5.5.1 trap instructions ................................................................................................... 53 5.5.2 illegal slot instructions ......................................................................................... 53 5.5.3 general illegal instructions................................................................................... 53 5.6 when exception sources are not accepted ..................................................................... 54 5.6.1 immediately after a delayed branch instruction.................................................. 54 5.6.2 immediately after an interrupt-disabled instruction ............................................ 54 5.7 stack status after exception processing ends ................................................................... 55 5.8 notes on use ............................................................................................................... ....... 56 5.8.1 value of stack pointer (sp).................................................................................. 56 5.8.2 value of vector base register (vbr).................................................................. 56 5.8.3 address errors caused by stacking of address error exception processing ...... 56 section 6 interrupt controller (intc) ......................................................................... 57 6.1 overview................................................................................................................... ......... 57 6.1.1 features ................................................................................................................. 57 6.1.2 block diagram...................................................................................................... 58 6.1.3 pin configuration.................................................................................................. 59 6.1.4 register configuration.......................................................................................... 59 6.2 interrupt sources.......................................................................................................... ...... 60 6.2.1 nmi interrupts ...................................................................................................... 60 6.2.2 irq interrupts ....................................................................................................... 60 6.2.3 on-chip peripheral module interrupts ................................................................. 61 6.2.4 interrupt exception vectors and priority rankings.............................................. 61 6.3 description of registers................................................................................................... .. 64 6.3.1 interrupt priority registers a? (ipra?prh)................................................... 64 6.3.2 interrupt control register (icr) .......................................................................... 65 6.3.3 irq status register (isr) .................................................................................... 66 6.4 interrupt operation ........................................................................................................ .... 68 6.4.1 interrupt sequence ................................................................................................ 68 iii 6.4.2 stack after interrupt exception processing........................................................... 70 6.5 interrupt response time.................................................................................................... 70 section 7 bus state controller (bsc) .......................................................................... 73 7.1 overview................................................................................................................... ......... 73 7.1.1 features ................................................................................................................. 73 7.1.2 block diagram...................................................................................................... 74 7.1.3 pin configuration.................................................................................................. 75 7.1.4 register configuration.......................................................................................... 75 7.1.5 address map ......................................................................................................... 76 7.2 description of registers................................................................................................... .. 77 7.2.1 bus control register 2 (bcr2)............................................................................ 77 7.2.2 wait control register 1 (wcr1) ......................................................................... 80 7.3 accessing ordinary space ................................................................................................. 82 7.3.1 basic timing......................................................................................................... 82 7.3.2 wait state control ................................................................................................ 83 7.3.3 cs assert period extension.................................................................................. 85 7.4 waits between access cycles............................................................................................ 86 7.4.1 prevention of data bus conflicts ......................................................................... 86 7.4.2 simplification of bus cycle start detection ........................................................ 87 7.5 memory connection examples.......................................................................................... 88 section 8 multifunction timer pulse unit (mtu) .................................................. 89 8.1 overview.................................................................................................................... ........ 89 8.1.1 features ................................................................................................................. 8 9 8.1.2 block diagram...................................................................................................... 92 8.1.3 pin configuration.................................................................................................. 93 8.1.4 register configuration.......................................................................................... 94 8.2 mtu register descriptions ............................................................................................... 95 8.2.1 timer control register (tcr).............................................................................. 95 8.2.2 timer mode register (tmdr)............................................................................. 99 8.2.3 timer i/o control register (tior)...................................................................... 100 8.2.4 timer interrupt enable register (tier)............................................................... 107 8.2.5 timer status register (tsr) ................................................................................ 109 8.2.6 timer counters (tcnt) ....................................................................................... 111 8.2.7 timer general register (tgr) ............................................................................. 112 8.2.8 timer start register (tstr) ................................................................................ 112 8.2.9 timer synchro register (tsyr) .......................................................................... 113 8.3 bus master interface ........................................................................................................ .. 114 8.3.1 16-bit registers .................................................................................................... 114 8.3.2 8-bit registers ...................................................................................................... 114 8.4 operation................................................................................................................... ......... 116 8.4.1 overview............................................................................................................... 116 iv 8.4.2 basic functions..................................................................................................... 116 8.4.3 synchronous operation ........................................................................................ 122 8.4.4 buffer operation ................................................................................................... 124 8.4.5 cascade connection mode ................................................................................... 127 8.4.6 pwm mode .......................................................................................................... 128 8.5 interrupts .................................................................................................................. .......... 133 8.5.1 interrupt sources and priority ranking ................................................................ 133 8.5.2 a/d converter activation..................................................................................... 134 8.6 operation timing ............................................................................................................ ... 135 8.6.1 input/output timing ............................................................................................. 135 8.6.2 interrupt signal timing ........................................................................................ 139 8.7 notes and precautions....................................................................................................... . 141 8.8 mtu output pin initialization ........................................................................................... 150 8.8.1 operating modes .................................................................................................. 150 8.8.2 reset start operation............................................................................................ 151 8.8.3 operation in case of re-setting due to error during operation, etc. ................ 151 8.8.4 overview of initialization procedures and mode transitions in case of error during operation, etc........................................................................................... 152 section 9 8-bit timer 1 (tim1) .................................................................................... 163 9.1 overview.................................................................................................................... ........ 163 9.1.1 features ................................................................................................................. 1 63 9.1.2 block diagram...................................................................................................... 164 9.1.3 register configuration.......................................................................................... 165 9.2 register descriptions ....................................................................................................... .. 165 9.2.1 timer 1 counter (t1cnt).................................................................................... 165 9.2.2 timer 1 control/status register (t1csr)............................................................ 166 9.2.3 notes on register access...................................................................................... 167 9.3 operation................................................................................................................... ......... 168 9.3.1 interval timer operation ...................................................................................... 168 9.3.2 timing of overflow flag (ovf) setting.............................................................. 169 9.4 usage notes ................................................................................................................. ...... 170 9.4.1 contention between timer 1 counter (tcnt) write and increment .................. 170 9.4.2 rewriting bits cks2 to cks0 ............................................................................. 170 section 10 8-bit timer 2 (tim2) .................................................................................... 171 10.1 overview................................................................................................................... ......... 171 10.1.1 features ................................................................................................................. 171 10.1.2 block diagram...................................................................................................... 172 10.1.3 register configuration.......................................................................................... 172 10.2 register descriptions ...................................................................................................... ... 173 10.2.1 timer 2 control/status register (t2csr)............................................................ 173 10.2.2 timer 2 counter (t2cnt).................................................................................... 174 v 10.2.3 timer 2 constant register (t2cor).................................................................... 175 10.3 operation.................................................................................................................. .......... 176 10.3.1 cyclic count operation ........................................................................................ 176 10.3.2 t2cnt count timing .......................................................................................... 176 10.4 interrupts ................................................................................................................. ........... 177 10.4.1 interrupt source .................................................................................................... 177 10.4.2 timing of compare match flag setting ............................................................... 177 10.4.3 timing of compare match flag clearing ............................................................ 178 section 11 compare match timer (cmt) .................................................................... 179 11.1 overview................................................................................................................... ......... 179 11.1.1 features ................................................................................................................. 179 11.1.2 block diagram...................................................................................................... 180 11.1.3 register configuration.......................................................................................... 181 11.2 register descriptions ...................................................................................................... ... 182 11.2.1 compare match timer start register (cmstr).................................................. 182 11.2.2 compare match timer control/status register (cmcsr).................................. 183 11.2.3 compare match timer counter (cmcnt).......................................................... 184 11.2.4 compare match timer constant register (cmcor) .......................................... 185 11.3 operation.................................................................................................................. .......... 185 11.3.1 period count operation ........................................................................................ 185 11.3.2 cmcnt count timing......................................................................................... 186 11.4 interrupts ................................................................................................................. ........... 186 11.4.1 interrupt sources................................................................................................... 186 11.4.2 compare match flag set timing.......................................................................... 186 11.4.3 compare match flag clear timing...................................................................... 187 11.5 notes on use ............................................................................................................... ....... 188 11.5.1 contention between cmcnt write and compare match ................................... 188 11.5.2 contention between cmcnt word write and incrementation ........................... 189 11.5.3 contention between cmcnt byte write and incrementation ............................ 190 section 12 serial communication interface (sci) ..................................................... 191 12.1 overview................................................................................................................... ......... 191 12.1.1 features ................................................................................................................. 191 12.1.2 block diagram...................................................................................................... 192 12.1.3 pin configuration.................................................................................................. 192 12.1.4 register configuration.......................................................................................... 193 12.2 register descriptions ...................................................................................................... ... 193 12.2.1 receive shift register (rsr) ............................................................................... 193 12.2.2 receive data register (rdr)............................................................................... 194 12.2.3 transmit shift register (tsr).............................................................................. 194 12.2.4 transmit data register (tdr) ............................................................................ 194 12.2.5 serial mode register (smr) ................................................................................ 195 vi 12.2.6 serial control register (scr) .............................................................................. 197 12.2.7 serial status register (ssr) ................................................................................. 199 12.2.8 bit rate register (brr) ....................................................................................... 203 12.3 operation.................................................................................................................. .......... 211 12.3.1 overview............................................................................................................... 21 1 12.3.2 operation in asynchronous mode........................................................................ 212 12.3.3 multiprocessor communication............................................................................ 221 12.4 interrupt.................................................................................................................. ............ 228 12.5 notes on use ............................................................................................................... ....... 229 section 13 a/d converter (a/d) ..................................................................................... 231 13.1 overview................................................................................................................... ......... 231 13.1.1 features ................................................................................................................. 231 13.1.2 block diagram...................................................................................................... 232 13.1.3 pin configuration.................................................................................................. 233 13.1.4 register configuration.......................................................................................... 234 13.2 register descriptions ...................................................................................................... ... 234 13.2.1 a/d data registers a? (addra?ddrd) .................................................... 234 13.2.2 a/d control/status register (adcsr) ................................................................ 235 13.2.3 a/d control register (adcr) ............................................................................. 237 13.3 cpu interface.............................................................................................................. ....... 238 13.4 operation.................................................................................................................. .......... 240 13.4.1 single mode (scan = 0) ..................................................................................... 240 13.4.2 scan mode (scan = 1)........................................................................................ 242 13.4.3 input sampling and a/d conversion time .......................................................... 244 13.4.4 mtu trigger input timing .................................................................................. 246 13.5 a/d conversion precision definitions .............................................................................. 246 13.6 notes on use ............................................................................................................... ....... 248 13.6.1 analog voltage settings ....................................................................................... 248 13.6.2 handling of analog input pins ............................................................................. 248 section 14 pin function controller ................................................................................. 251 14.1 overview................................................................................................................... ......... 251 14.2 register configuration ..................................................................................................... .. 251 14.3 register descriptions ...................................................................................................... ... 252 14.3.1 port a i/o register h (paiorh)......................................................................... 252 14.3.2 port e i/o register (peior) ................................................................................ 252 14.3.3 port e control register 2 (pecr2) ...................................................................... 253 section 15 i/o ports (i/o) .................................................................................................. 255 15.1 overview................................................................................................................... ......... 255 15.2 port a ..................................................................................................................... ............ 255 15.2.1 register configuration.......................................................................................... 255 vii 15.2.2 port a data register h (padrh)........................................................................ 256 15.3 port e..................................................................................................................... ............. 257 15.3.1 register configuration.......................................................................................... 257 15.3.2 port e data register (pedr)................................................................................ 258 section 16 ram .................................................................................................................... 261 16.1 overview................................................................................................................... ......... 261 section 17 electrical characteristics .............................................................................. 263 17.1 absolute maximum ratings .............................................................................................. 263 17.2 dc characteristics ......................................................................................................... .... 264 17.3 ac characteristics ......................................................................................................... .... 266 17.3.1 clock timing ........................................................................................................ 266 17.3.2 control signal timing .......................................................................................... 268 17.3.3 bus timing ........................................................................................................... 270 17.3.4 multifunction timer pulse unit timing ............................................................... 274 17.3.5 i/o port timing..................................................................................................... 275 17.3.6 serial communication interface timing .............................................................. 276 17.3.7 a/d converter timing.......................................................................................... 277 17.3.8 measurement conditions for ac characteristic................................................... 278 17.4 a/d converter characteristics ........................................................................................... 279 appendix a on-chip supporting module registers ................................................. 281 appendix b pin states ........................................................................................................ 285 b.1 pin states.................................................................................................................. .......... 285 b.2 bus related signal pin states ............................................................................................ 286 appendix c package dimensions ................................................................................... 287 1 section 1 SH7011 overview 1.1 SH7011 overview the SH7011 cmos single-chip microprocessors integrate a hitachi-original architecture, high- speed cpu with peripheral functions required for system configuration. the cpu has a risc-type instruction set . most instructions can be executed in one clock cycle, which greatly improves instruction execution speed . in addition, the 32-bit internal-bus architecture enhances data processing power. with this cpu, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds. in addition, the SH7011 includes on-chip peripheral functions necessary for system configuration, such as large-capacity rom, timers, a serial communication interface (sci), an a/d converter, an interrupt controller, and i/o ports. memory or peripheral lsis can be connected efficiently with an external memory access support function. this greatly reduces system cost. 1.1.1 SH7011 features cpu: original hitachi architecture 32-bit internal data bus general-register machine ? sixteen 32-bit general registers ? three 32-bit control registers ? four 32-bit system registers risc-type instruction set ? instruction length: 16-bit fixed length for improved code efficiency ? load-store architecture (basic operations are executed between registers) ? delayed branch instructions reduce pipeline disruption during branch ? instruction set based on c language instruction execution time: one instruction/cycle (50 ns/instruction at 20-mhz operation) address space: architecture supports 4 gbytes on-chip multiplier: multiplication operations (32 bits 32 bits ? 64 bits) and multiplication/accumulation operations (32 bits 32 bits + 64 bits ? 64 bits) executed in two to four cycles five-stage pipeline 2 interrupt controller (intc): nine external interrupt pins (nmi, irq0 to irq7 ) twenty-two internal interrupt sources sixteen programmable priority levels bus state controller (bsc): supports external extended memory access ? 16-bit external data bus memory address space divided into four areas (four areas of sram space) with the following settable features: ? number of wait cycles (0 to 3 cycles) ? outputs chip-select signals for each area wait cycles can be inserted using an external wait signal multifunction timer pulse unit (mtu): maximum 6 types of waveform output or maximum 6 types of pulse i/o processing possible based on 16-bit timer, 3 channels 8 dual-use output compare/input capture registers 8 independent comparators 6 types of counter input clock input capture function pulse output mode ? one shot, toggle, pwm multiple counter synchronization function compare match timer (cmt) (two channels): 16-bit free-running counter one compare register generates an interrupt request upon compare match 8-bit timers (tim1, tim2) (two channels): 8-bit interval timer function interrupt generated on counter overflow (tim1) interrupt generated on compare match (tim2) 3 serial communication interface (sci) (one channel): asynchronous mode can transmit and receive simultaneously (full duplex) on-chip dedicated baud rate generator multiprocessor communication function i/o ports: input/output: 11 a/d converter: 10 bits 7 channels sample & hold function large capacity on-chip memory: ram: 4 kbytes operating modes: processing states ? program execution state ? exception processing state power-down modes ? sleep mode clock pulse generator (cpg): on-chip clock pulse generator package: 100-pin plastic tqfp (tfp-100b) 4 1.2 block diagram pa19 pa18 pe14 pe13 pe12 wait ck rd wrh wrl cs3 cs2 cs1 cs0 rxd txd nmi irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d2 d1 d0 avss an6 an5 an4 an3 an2 an1 an0 tioc2b/pe7 tioc2a/pe6 tioc1b/pe5 tioc1a/pe4 tioc0c/pe2 tioc0a/pe0 res extal xtal vcc vcc vcc vcc vcc vcc vcc vss vss vss vss vss vss vss vss vss vss vss vss vss serial communi- cation interface ( 1 channel) interrupt controller timers 16-bit multifunctional timers 3, 16-bit compare match timers 2, 8-bit timers 2 bus state controller a/d converter cpu avcc ram 4 kbytes data address : peripheral address bus : peripheral data bus : internal address bus : internal upper data bus : internal lower data bus figure 1.1 block diagram of the SH7011 5 1.3 pin arrangement and pin functions 1.3.1 pin arrangment ck res pe0/tioc0a pe2/tioc0c vcc pe4/tioc1a pe5/tioc1b pe6/tioc2a vss an0 an1 an2 an3 an4 an5 avss an6 avcc vss rxd txd vcc pe7tioc2b pe12 pe13 tfp-100b SH7011 pe14 vss a1 a2 a3 a4 a5 vss a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 vcc a17 vss pa19 pa18 vss vss vcc wait vcc nmi vss extal vss xtal vss d0 d1 d2 d3 d4 vss d5 vcc d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 irq0 vss irq1 irq2 irq3 irq4 irq5 irq6 irq7 cs2 cs3 cs0 cs1 wrl wrh rd vss a21 vcc a20 a19 a18 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 figure 1.2 SH7011 pin arrangement (tfp-100: top view) 6 1.3.2 pin functions table 1.1 lists the pin functions. table 1.1 pin functions classification symbol i/o name function power supply v cc i supply connects to power supply. connect all v cc pins to the system supply. no operation will occur if there are any open pins. v ss i ground connects to ground. connect all v ss pins to the system ground. no operation will occur if there are any open pins. clock extal i external clock connect a crystal oscillator. also, an external clock can be input to the extal pin. xtal i crystal connect a crystal oscillator. ck o system clock supplies the system clock to peripheral devices. system control res i power-on reset power-on reset when low interrupts nmi i non-maskable interrupt non-maskable interrupt request pin. enables selection of whether to accept on the rising or falling edge. irq0 e irq7 i interrupt requests 0e7 maskable interrupt request pins. allows selection of level input and edge input. address bus a1ea21 o address bus outputs addresses. data bus d0ed15 i/o data bus 16-bit bidirectional data bus. bus control cs0 to cs3 o chip selects 0e3 chip select signals for external memory or devices. rd o read indicates reading from an external device. wrh o upper write indicates writing the upper 8 bits (15e 8) of external data. wrl o lower write indicates writing the lower 8 bits (7e0) of external data. wait i wait input causes insertion of wait cycles into the bus cycle during external space access. 7 table 1.1 pin functions (cont) classification symbol i/o name function multifunction timer/pulse unit (mtu) tioc0a tioc0c i/o mtu input capture/output compare (channel 0) channel 0 input capture input/output compare output/pwm output pins. tioc1a tioc1b i/o mtu input capture/output compare (channel 1) channel 1 input capture input/output compare output/pwm output pins. tioc2a tioc2b i/o mtu input capture/output compare (channel 2) channel 2 input capture input/output compare output/pwm output pins. serial communication interface (sci) txd o transmit data transmit data output pins. rxd i receive data receive data input pins. a/d converter av cc i analog supply analog supply; connected to v cc . av ss i analog ground analog supply; connected to v ss . an0 to an6 i analog input analog signal input pins. i/o ports pa18, 19 i/o port output enable input pin for port pin drive control when general use ports are established as output. pe0, 2, 4, to 7, 12 to 14 i/o general purpose port general purpose input/output port pins. each bit can be designated for input/output. 9 section 2 cpu 2.1 register configuration the register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. 2.1.1 general registers (rn) the sixteen 32-bit general registers (rn) are numbered r0?15. general registers are used for data processing and address calculation. r0 is also used as an index register. several instructions have r0 fixed as their only usable register. r15 is used as the hardware stack pointer (sp). saving and recovering the status register (sr) and program counter (pc) in exception processing is accomplished by referencing the stack using r15. figure 2.1 shows the general registers. r0* 1 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15, sp (hardware stack pointer)* 2 0 31 1. 2. r0 functions as an index register in the indirect indexed register addressing mode and indirect indexed gbr addressing mode. in some instructions, r0 functions as a fixed source register or destination register. r15 functions as a hardware stack pointer (sp) during exception processing. notes: figure 2.1 general registers 10 2.1.2 control registers the 32-bit control registers consist of the 32-bit status register (sr), global base register (gbr), and vector base register (vbr). the status register indicates processing states. the global base register functions as a base address for the indirect gbr addressing mode to transfer data to the registers of on-chip peripheral modules. the vector base register functions as the base address of the exception processing vector area (including interrupts). figure 2.2 shows a control register. 9876543210 mqi3 i2 i1 i0 st 0 0 31 31 gbr vbr sr 31 s bit: used by the mac instruction. reserved bits. this bit always read 0. the write value should always be 0. reserved bits. 0 is read. write only. bits i0?3: interrupt mask bits. m and q bits: used by the div0u, div0s, and div1 instructions. global base register (gbr): indicates the base address of the indirect gbr addressing mode. the indirect gbr addressing mode is used in data transfer for on-chip peripheral modules register areas and in logic operations. vector base register (vbr): stores the base address of the exception processing vector area. sr: status register t bit: the movt, cmp/cond, tas, tst, bt (bt/s), bf (bf/s), sett, and clrt instructions use the t bit to indicate true (1) or false (0). the addv, addc, subv, subc, negc, div0u, div0s, div1, shar, shal, shlr, shll, rotr, rotl, rotcr, and rotcl instructions also use the t bit to indicate carry/borrow or overflow/underflow. figure 2.2 control registers 11 2.1.3 system registers system registers consist of four 32-bit registers: high and low multiply and accumulate registers (mach and macl), the procedure register (pr), and the program counter (pc). the multiply and accumulate registers store the results of multiply and accumulate operations. the procedure register stores the return address from the subroutine procedure. the program counter stores program addresses to control the flow of the processing. figure 2.3 shows a system register. macl pr pc mach 31 0 0 0 31 31 multiply and accumulate (mac) registers high and low (mach, macl): stores the results of multiply and accumulate operations. procedure register (pr): stores a return address from a subroutine procedure. program counter (pc): indicates the fourth byte (second instruction) after the current instruction. figure 2.3 system registers 2.1.4 initial values of registers table 2.1 lists the values of the registers after reset. table 2.1 initial values of registers classification register initial value general registers r0?14 undefined r15 (sp) value of the stack pointer in the vector address table control registers sr bits i3?0 are 1111 (h'f), reserved bits are 0, and other bits are undefined gbr undefined vbr h'00000000 system registers mach, macl, pr undefined pc value of the program counter in the vector address table 12 2.2 data formats 2.2.1 data format in registers register operands are always longwords (32 bits). when the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure 2.4). 31 0 longword figure 2.4 longword operand 2.2.2 data format in memory memory data formats are classified into bytes, words, and longwords. byte data can be accessed from any address, but an address error will occur if you try to access word data starting from an address other than 2n or longword data starting from an address other than 4n. in such cases, the data accessed cannot be guaranteed. the hardware stack area, referred to by the hardware stack pointer (sp, r15), uses only longword data starting from address 4n because this area holds the program counter and status register (figure 2.5). 31 0 15 23 7 byte byte byte byte word word address 2n address 4n longword address m address m + 2 address m + 1 address m + 3 figure 2.5 byte, word, and longword alignment 2.2.3 immediate data format byte (8 bit) immediate data resides in an instruction code. immediate data accessed by the mov, add, and cmp/eq instructions is sign-extended and handled in registers as longword data. immediate data accessed by the tst, and, or, and xor instructions is zero-extended and handled as longword data. consequently, and instructions with immediate data always clear the upper 24 bits of the destination register. 13 word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. an immediate data transfer instruction (mov) accesses the memory table using the pc relative addressing mode with displacement. 2.3 instruction features 2.3.1 risc-type instruction set all instructions are risc type. this section details their functions. 16-bit fixed length : all instructions are 16 bits long, increasing program code efficiency. one instruction per cycle : the microprocessor can execute basic instructions in one cycle using the pipeline system. instructions are executed in 50 ns at 20 mhz. data length : longword is the standard data length for all operations. memory can be accessed in bytes, words, or longwords. byte or word data accessed from memory is sign-extended and handled as longword data. immediate data is sign-extended for arithmetic operations or zero- extended for logic operations. it also is handled as longword data (table 2.2). table 2.2 sign extension of word data SH7011 cpu description example of conventional cpu mov.w @(disp,pc),r1 add r1,r0 ......... .data.w h'1234 data is sign-extended to 32 bits, and r1 becomes h'00001234. it is next operated upon by an add instruction. add.w #h'1234,r0 note: @(disp, pc) accesses the immediate data. load-store architecture : basic operations are executed between registers. for operations that involve memory access, data is loaded to the registers and executed (load-store architecture). instructions such as and that manipulate bits, however, are executed directly in memory. delayed branch instructions : unconditional branch instructions are delayed. executing the instruction that follows the branch instruction and then branching reduces pipeline disruption during branching (table 2.3). there are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions. 14 table 2.3 delayed branch instructions SH7011 cpu description example of conventional cpu bra trget add r1,r0 executes an add before branching to trget add.w r1,r0 bra trget multiplication/accumulation operation : 16-bit 16-bit ? 32-bit multiplication operations are executed in one to two cycles. 16-bit 16-bit + 64-bit ? 64-bit multiplication/accumulation operations are executed in two to three cycles. 32-bit 32-bit ? 64-bit and 32-bit 32-bit + 64bit ? 64-bit multiplication/accumulation operations are executed in two to four cycles. t bit : the t bit in the status register changes according to the result of the comparison, and in turn is the condition (true/false) that determines if the program will branch. the number of instructions that change the t bit is kept to a minimum to improve the processing speed (table 2.4). table 2.4 t bit SH7011 cpu description example of conventional cpu cmp/ge r1,r0 bt trget0 bf trget1 t bit is set when r0 3 r1. the program branches to trget0 when r0 3 r1 and to trget1 when r0 16 2.3.2 addressing modes table 2.8 describes addressing modes and effective address calculation. table 2.8 addressing modes and effective addresses addressing mode instruction format effective addresses calculation equation direct register addressing rn the effective address is register rn. (the operand is the contents of register rn.) indirect register addressing @rn the effective address is the content of register rn. rn rn rn post-increment indirect register addressing @rn+ the effective address is the content of register rn. a constant is added to the content of rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. rn rn 1/2/4 + rn + 1/2/4 rn (after the instruction executes) byte: rn + 1 ? rn word: rn + 2 ? rn longword: rn + 4 ? rn pre-decrement indirect register addressing @?n the effective address is the value obtained by subtracting a constant from rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. rn 1/2/4 rn ?1/2/4 rn ?1/2/4 byte: rn ?1 ? rn word: rn e 2 ? rn longword: rn e 4 ? rn (instruction executed with rn after calculation) 17 table 2.8 addressing modes and effective addresses (cont) addressing mode instruction format effective addresses calculation equation indirect register addressing with displacement @(disp:4, rn) the effective address is rn plus a 4-bit displacement (disp). the value of disp is zero- extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. rn rn + disp 1/2/4 + 1/2/4 disp (zero-extended) byte: rn + disp word: rn + disp 2 longword: rn + disp 4 indirect indexed register addressing @(r0, rn) the effective address is the rn value plus r0. rn r0 rn + r0 + rn + r0 indirect gbr addressing with displacement @(disp:8, gbr) the effective address is the gbr value plus an 8-bit displacement (disp). the value of disp is zero- extended, and remains the same for a byte opera- tion, is doubled for a word operation, and is quadrupled for a longword operation. gbr 1/2/4 gbr + disp 1/2/4 + disp (zero-extended) byte: gbr + disp word: gbr + disp 2 longword: gbr + disp 4 18 table 2.8 addressing modes and effective addresses (cont) addressing mode instruction format effective addresses calculation equation indirect indexed gbr addressing @(r0, gbr) the effective address is the gbr value plus the r0. gbr r0 gbr + r0 + gbr + r0 pc relative addressing with displacement @(disp:8, pc) the effective address is the pc value plus an 8-bit displacement (disp). the value of disp is zero- extended, and is doubled for a word operation, and quadrupled for a longword operation. for a longword?peration, the lowest two bits of the pc value are masked. pc h'fffffffc pc + disp 2 or pc & h'fffffffc + disp 4 + 2/4 & (for longword) disp (zero-extended) word: pc + disp 2 longword: pc & h'fffffffc + disp 4 19 table 2.8 addressing modes and effective addresses (cont) addressing mode instruction format effective addresses calculation equation pc relative addressing disp:8 the effective address is the pc value sign-extended with an 8-bit displacement (disp), doubled, and added?o the pc value. pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2 disp:12 the effective address is the pc value sign-extended with a 12-bit displacement (disp), doubled, and added?o the pc value. pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2 rn the effective address is the register pc value plus rn. pc rn pc + rn + pc + rn immediate addressing #imm:8 the 8-bit immediate data (imm) for the tst, and, or, and xor instructions are zero-extended. #imm:8 the 8-bit immediate data (imm) for the mov, add, and cmp/eq instructions are sign-extended. #imm:8 the 8-bit immediate data (imm) for the trapa instruction is zero-extended and is quadrupled. 20 2.3.3 instruction format table 2.9 lists the instruction formats for the source operand and the destination operand. the meaning of the operand depends on the instruction code. the symbols are used as follows: xxxx: instruction code mmmm: source register nnnn: destination register iiii: immediate data dddd: displacement table 2.9 instruction formats instruction formats source operand destination operand example 0 format xxxx xxxx xxxx xxxx 15 0 nop n format nnnn: direct register movt rn xxxx xxxx xxxx nnnn 15 0 control register or system register nnnn: direct register sts mach,rn control register or system register nnnn: indirect pre- decrement register stc.l sr,@-rn m format mmmm: direct register control register or system register ldc rm,sr xxxx mmmm xxxx xxxx 15 0 mmmm: indirect post-increment register control register or system register ldc.l @rm+,sr mmmm: direct register jmp @rm mmmm: pc relative using rm braf rm 21 table 2.9 instruction formats (cont) instruction formats source operand destination operand example nm format mmmm: direct register nnnn: direct register add rm,rn nnnn xxxx xxxx 15 0 mmmm mmmm: direct register nnnn: indirect register mov.l rm,@rn mmmm: indirect post-increment register (multiply/ accumulate) nnnn*: indirect post-increment register (multiply/ accumulate) mach, macl mac.w @rm+,@rn+ mmmm: indirect post-increment register nnnn: direct register mov.l @rm+,rn mmmm: direct register nnnn: indirect pre- decrement register mov.l rm,@-rn mmmm: direct register nnnn: indirect indexed register mov.l rm,@(r0,rn) md format xxxx dddd 15 0 mmmm xxxx mmmmdddd: indirect register with displacement r0 (direct register) mov.b @(disp,rm),r0 nd4 format xxxx xxxx dddd 15 0 nnnn r0 (direct register) nnnndddd: indirect register with displacement mov.b r0,@(disp,rn) nmd format nnnn xxxx dddd 15 0 mmmm mmmm: direct register nnnndddd: indirect register with displacement mov.l rm,@(disp,rn) mmmmdddd: indirect register with displacement nnnn: direct register mov.l @(disp,rm),rn note: in multiply/accumulate instructions, nnnn is the source register. 22 table 2.9 instruction formats (cont) instruction formats source operand destination operand example d format dddd xxxx 15 0 xxxx dddd dddddddd: indirect gbr with displacement r0 (direct register) mov.l @(disp,gbr),r0 r0(direct register) dddddddd: indirect gbr with displacement mov.l r0,@(disp,gbr) dddddddd: pc relative with displacement r0 (direct register) mova @(disp,pc),r0 dddddddd: pc relative bf label d12 format dddd xxxx 15 0 dddd dddd dddddddddddd: pc relative bra label (label = disp + pc) nd8 format dddd nnnn xxxx 15 0 dddd dddddddd: pc relative with displacement nnnn: direct register mov.l @(disp,pc),rn i format iiiiiiii: immediate indirect indexed gbr and.b #imm,@(r0,gbr) xxxx xxxx i i i i 15 0 i i i i iiiiiiii: immediate r0 (direct register) and #imm,r0 iiiiiiii: immediate trapa #imm ni format nnnn i i i i xxxx 15 0 i i i i iiiiiiii: immediate nnnn: direct register add #imm,rn 23 2.4 instruction set by classification table 2.10 classification of instructions classification types operation code function no. of instructions data transfer 5 mov data transfer, immediate data transfer, peripheral module data transfer, structure data transfer 39 mova effective address transfer movt t bit transfer swap swap of upper and lower bytes xtrct extraction of the middle of registers connected arithmetic 21 add binary addition 33 operations addc binary addition with carry addv binary addition with overflow check cmp/cond comparison div1 division div0s initialization of signed division div0u initialization of unsigned division dmuls signed double-length multiplication dmulu unsigned double-length multiplication dt decrement and test exts sign extension extu zero extension mac multiply/accumulate, double-length multiply/accumulate operation mul double-length multiply operation muls signed multiplication mulu unsigned multiplication neg negation negc negation with borrow sub binary subtraction subc binary subtraction with borrow subv binary subtraction with underflow 24 table 2.10 classification of instructions (cont) classification types operation code function no. of instructions logic 6 and logical and 14 operations not bit inversion or logical or tas memory test and bit set tst logical and and t bit set xor exclusive or shift 10 rotl one-bit left rotation 14 rotr one-bit right rotation rotcl one-bit left rotation with t bit rotcr one-bit right rotation with t bit shal one-bit arithmetic left shift shar one-bit arithmetic right shift shll one-bit logical left shift shlln n-bit logical left shift shlr one-bit logical right shift shlrn n-bit logical right shift branch 9 bf conditional branch, conditional branch with delay (branch when t = 0) 11 bt conditional branch, conditional branch with delay (branch when t = 1) bra unconditional branch braf unconditional branch bsr branch to subroutine procedure bsrf branch to subroutine procedure jmp unconditional branch jsr branch to subroutine procedure rts return from subroutine procedure 25 table 2.10 classification of instructions (cont) classification types operation code function no. of instructions system 11 clrt t bit clear 31 control clrmac mac register clear ldc load to control register lds load to system register nop no operation rte return from exception processing sett t bit set sleep shift into power-down mode stc storing control register data sts storing system register data trapa trap exception handling total: 62 142 table 2.11 shows the format used in tables 2.12 to 2.17, which list instruction codes, operation, and execution states in order by classification. 26 table 2.11 instruction code format item format explanation instruction op.sz src,dest op: operation code sz: size (b: byte, w: word, or l: longword) src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement* 1 instruction code msb ? lsb mmmm: source register nnnn: destination register 0000: r0 0001: r1 . . . 1111: r15 iiii: immediate data dddd: displacement operation ? , ? direction of transfer (xx) memory operand m/q/t flag bits in the sr & logical and of each bit | logical or of each bit ^ exclusive or of each bit ~ logical not of each bit < 27 table 2.12 data transfer instructions instruction instruction code operation execu- tion cycles t bit mov #imm,rn 1110nnnniiiiiiii #imm ? sign extension ? rn 1? mov.w @(disp,pc),rn 1001nnnndddddddd (disp 2 + pc) ? sign extension ? rn 1? mov.l @(disp,pc),rn 1101nnnndddddddd (disp 4 + pc) ? rn 1 ? mov rm,rn 0110nnnnmmmm0011 rm ? rn 1 ? mov.b rm,@rn 0010nnnnmmmm0000 rm ? (rn) 1 ? mov.w rm,@rn 0010nnnnmmmm0001 rm ? (rn) 1 ? mov.l rm,@rn 0010nnnnmmmm0010 rm ? (rn) 1 ? mov.b @rm,rn 0110nnnnmmmm0000 (rm) ? sign extension ? rn 1? mov.w @rm,rn 0110nnnnmmmm0001 (rm) ? sign extension ? rn 1? mov.l @rm,rn 0110nnnnmmmm0010 (rm) ? rn 1 ? mov.b rm,@?n 0010nnnnmmmm0100 rn? ? rn, rm ? (rn) 1 ? mov.w rm,@?n 0010nnnnmmmm0101 rn? ? rn, rm ? (rn) 1 ? mov.l rm,@?n 0010nnnnmmmm0110 rn? ? rn, rm ? (rn) 1 ? mov.b @rm+,rn 0110nnnnmmmm0100 (rm) ? sign extension ? rn,rm + 1 ? rm 1? mov.w @rm+,rn 0110nnnnmmmm0101 (rm) ? sign extension ? rn,rm + 2 ? rm 1? mov.l @rm+,rn 0110nnnnmmmm0110 (rm) ? rn,rm + 4 ? rm 1 ? mov.b r0,@(disp,rn) 10000000nnnndddd r0 ? (disp + rn) 1 ? mov.w r0,@(disp,rn) 10000001nnnndddd r0 ? (disp 2 + rn) 1 ? mov.l rm,@(disp,rn) 0001nnnnmmmmdddd rm ? (disp 4 + rn) 1 ? mov.b @(disp,rm),r0 10000100mmmmdddd (disp + rm) ? sign extension ? r0 1? mov.w @(disp,rm),r0 10000101mmmmdddd (disp 2 + rm) ? sign extension ? r0 1? mov.l @(disp,rm),rn 0101nnnnmmmmdddd (disp 4 + rm) ? rn 1 ? mov.b rm,@(r0,rn) 0000nnnnmmmm0100 rm ? (r0 + rn) 1 ? 28 table 2.12 data transfer instructions (cont) instruction instruction code operation execu- tion cycles t bit mov.w rm,@(r0,rn) 0000nnnnmmmm0101 rm ? (r0 + rn) 1 ? mov.l rm,@(r0,rn) 0000nnnnmmmm0110 rm ? (r0 + rn) 1 ? mov.b @(r0,rm),rn 0000nnnnmmmm1100 (r0 + rm) ? sign extension ? rn 1? mov.w @(r0,rm),rn 0000nnnnmmmm1101 (r0 + rm) ? sign extension ? rn 1? mov.l @(r0,rm),rn 0000nnnnmmmm1110 (r0 + rm) ? rn 1 ? mov.b r0,@(disp,gbr) 11000000dddddddd r0 ? (disp + gbr) 1 ? mov.w r0,@(disp,gbr) 11000001dddddddd r0 ? (disp 2 + gbr) 1 ? mov.l r0,@(disp,gbr) 11000010dddddddd r0 ? (disp 4 + gbr) 1 ? mov.b @(disp,gbr),r0 11000100dddddddd (disp + gbr) ? sign extension ? r0 1? mov.w @(disp,gbr),r0 11000101dddddddd (disp 2 + gbr) ? sign extension ? r0 1? mov.l @(disp,gbr),r0 11000110dddddddd (disp 4 + gbr) ? r0 1 ? mova @(disp,pc),r0 11000111dddddddd disp 4 + pc ? r0 1 ? movt rn 0000nnnn00101001 t ? rn 1 ? swap.b rm,rn 0110nnnnmmmm1000 rm ? swap the bottom two bytes ? rn 1? swap.w rm,rn 0110nnnnmmmm1001 rm ? swap two consecutive words ? rn 1? xtrct rm,rn 0010nnnnmmmm1101 rm: middle 32 bits of rn ? rn 1? 29 table 2.13 arithmetic operation instructions instruction instruction code operation execu- tion cycles t bit add rm,rn 0011nnnnmmmm1100 rn + rm ? rn 1 ? add #imm,rn 0111nnnniiiiiiii rn + imm ? rn 1 ? addc rm,rn 0011nnnnmmmm1110 rn + rm + t ? rn, carry ? t 1 carry addv rm,rn 0011nnnnmmmm1111 rn + rm ? rn, overflow ? t 1 overflow cmp/eq #imm,r0 10001000iiiiiiii if r0 = imm, 1 ? t 1 comparison result cmp/eq rm,rn 0011nnnnmmmm0000 if rn = rm, 1 ? t 1 comparison result cmp/hs rm,rn 0011nnnnmmmm0010 if rn 3 rm with unsigned data, 1 ? t 1 comparison result cmp/ge rm,rn 0011nnnnmmmm0011 if rn 3 rm with signed data, 1 ? t 1 comparison result cmp/hi rm,rn 0011nnnnmmmm0110 if rn > rm with unsigned data, 1 ? t 1 comparison result cmp/gt rm,rn 0011nnnnmmmm0111 if rn > rm with signed data, 1 ? t 1 comparison result cmp/pl rn 0100nnnn00010101 if rn > 0, 1 ? t 1 comparison result cmp/pz rn 0100nnnn00010001 if rn 3 0, 1 ? t 1 comparison result cmp/str rm,rn 0010nnnnmmmm1100 if rn and rm have an?quivalent byte, 1 ? t 1 comparison result div1 rm,rn 0011nnnnmmmm0100 single-step division (rn/rm) 1 calculation result div0s rm,rn 0010nnnnmmmm0111 msb of rn ? q, msb of rm ? m, m^q ? t 1 calculation result div0u 0000000000011001 0 ? m/q/t 1 0 30 table 2.13 arithmetic operation instructions (cont) instruction instruction code operation execu- tion cycles t bit dmuls.l rm,rn 0011nnnnmmmm1101 signed operation of rn rm ? mach, macl 32 32 ? 64 bit 2 to 4* ? dmulu.l rm,rn 0011nnnnmmmm0101 unsigned operation of rn rm ? mach, macl 32 32 ? 64 bit 2 to 4* ? dt rn 0100nnnn00010000 rn ?1 ? rn, when rn is 0, 1 ? t. when rn is nonzero, 0 ? t 1 comparison result exts.b rm,rn 0110nnnnmmmm1110 a byte in rm is sign- extended ? rn 1? exts.w rm,rn 0110nnnnmmmm1111 a word in rm is sign- extended ? rn 1? extu.b rm,rn 0110nnnnmmmm1100 a byte in rm is zero- extended ? rn 1? extu.w rm,rn 0110nnnnmmmm1101 a word in rm is zero- extended ? rn 1? mac.l @rm+,@rn+ 0000nnnnmmmm1111 signed operation of (rn) (rm) + mac ? mac 32 32 ? 64 bit 3/(2 to 4)* ? mac.w @rm+,@rn+ 0100nnnnmmmm1111 signed operation of (rn) (rm) + mac ? mac 16 16 + 64 ? 64 bit 3/(2)* ? mul.l rm,rn 0000nnnnmmmm0111 rn rm ? macl, 32 32 ? 32 bit 2 to 4* ? muls.w rm,rn 0010nnnnmmmm1111 signed operation of rn rm ? mac 16 16 ? 32 bit 1 to 3* ? mulu.w rm,rn 0010nnnnmmmm1110 unsigned operation of rn rm ? mac 16 16 ? 32 bit 1 to 3* ? neg rm,rn 0110nnnnmmmm1011 0?m ? rn 1 ? negc rm,rn 0110nnnnmmmm1010 0?m? ? rn, borrow ? t 1 borrow 31 table 2.13 arithmetic operation instructions (cont) instruction instruction code operation execu- tion cycles t bit sub rm,rn 0011nnnnmmmm1000 rn?m ? rn 1 ? subc rm,rn 0011nnnnmmmm1010 rn?m? ? rn, borrow ? t 1 borrow subv rm,rn 0011nnnnmmmm1011 rn?m ? rn, underflow ? t 1 overflow note: the normal minimum number of execution cycles. (the number in parentheses is the number of cycles when there is contention with following instructions.) table 2.14 logic operation instructions instruction instruction code operation execu- tion cycles t bit and rm,rn 0010nnnnmmmm1001 rn & rm ? rn 1 ? and #imm,r0 11001001iiiiiiii r0 & imm ? r0 1 ? and.b #imm,@(r0,gbr) 11001101iiiiiiii (r0 + gbr) & imm ? (r0+ gbr) 3? not rm,rn 0110nnnnmmmm0111 ~rm ? rn 1 ? or rm,rn 0010nnnnmmmm1011 rn | rm ? rn 1 ? or #imm,r0 11001011iiiiiiii r0 | imm ? r0 1 ? or.b #imm,@(r0,gbr) 11001111iiiiiiii (r0 + gbr) | imm ? (r0+ gbr) 3? tas.b @rn 0100nnnn00011011 if (rn) is 0, 1 ? t; 1 ? msb of (rn) 4 test result tst rm,rn 0010nnnnmmmm1000 rn & rm; if the result is 0, 1 ? t 1 test result tst #imm,r0 11001000iiiiiiii r0 & imm; if the result is 0, 1 ? t 1 test result tst.b #imm,@(r0,gbr) 11001100iiiiiiii (r0 + gbr) & imm; if the result is 0, 1 ? t 3 test result xor rm,rn 0010nnnnmmmm1010 rn ^ rm ? rn 1 ? xor #imm,r0 11001010iiiiiiii r0 ^ imm ? r0 1 ? xor.b #imm,@(r0,gbr) 11001110iiiiiiii (r0 + gbr) ^ imm ? (r0+ gbr) 3? 32 table 2.15 shift instructions instruction instruction code operation execu- tion cycles t bit rotl rn 0100nnnn00000100 t ? rn ? msb 1 msb rotr rn 0100nnnn00000101 lsb ? rn ? t 1 lsb rotcl rn 0100nnnn00100100 t ? rn ? t 1 msb rotcr rn 0100nnnn00100101 t ? rn ? t 1 lsb shal rn 0100nnnn00100000 t ? rn ? 0 1 msb shar rn 0100nnnn00100001 msb ? rn ? t 1 lsb shll rn 0100nnnn00000000 t ? rn ? 0 1 msb shlr rn 0100nnnn00000001 0 ? rn ? t 1 lsb shll2 rn 0100nnnn00001000 rn<<2 ? rn 1 ? shlr2 rn 0100nnnn00001001 rn>>2 ? rn 1 ? shll8 rn 0100nnnn00011000 rn<<8 ? rn 1 ? shlr8 rn 0100nnnn00011001 rn>>8 ? rn 1 ? shll16 rn 0100nnnn00101000 rn<<16 ? rn 1 ? shlr16 rn 0100nnnn00101001 rn>>16 ? rn 1 ? 33 table 2.16 branch instructions instruction instruction code operation exec. cycles t bit bf label 10001011dddddddd if t = 0, disp 2 + pc ? pc; if t = 1, nop 3/1* ? bf/s label 10001111dddddddd delayed branch, if t = 0, disp 2 + pc ? pc; if t = 1, nop 3/1* ? bt label 10001001dddddddd if t = 1, disp 2 + pc ? pc; if t = 0, nop 3/1* ? bt/s label 10001101dddddddd delayed branch, if t = 1, disp 2 + pc ? pc; if t = 0, nop 2/1* ? bra label 1010dddddddddddd delayed branch, disp 2 + pc ? pc 2? braf rm 0000mmmm00100011 delayed branch, rm + pc ? pc 2 ? bsr label 1011dddddddddddd delayed branch, pc ? pr, disp 2 + pc ? pc 2? bsrf rm 0000mmmm00000011 delayed branch, pc ? pr, rm+pc ? pc 2? jmp @rm 0100mmmm00101011 delayed branch, rm ? pc 2 ? jsr @rm 0100mmmm00001011 delayed branch, pc ? pr, rm ? pc 2? rts 0000000000001011 delayed branch, pr ? pc 2 ? note: one state when it does not branch. 34 table 2.17 system control instructions instruction instruction code operation exec. cycles t bit clrt 0000000000001000 0 ? t10 clrmac 0000000000101000 0 ? mach, macl 1 ? ldc rm,sr 0100mmmm00001110 rm ? sr 1 lsb ldc rm,gbr 0100mmmm00011110 rm ? gbr 1 ? ldc rm,vbr 0100mmmm00101110 rm ? vbr 1 ? ldc.l @rm+,sr 0100mmmm00000111 (rm) ? sr, rm + 4 ? rm 3 lsb ldc.l @rm+,gbr 0100mmmm00010111 (rm) ? gbr, rm + 4 ? rm 3 ? ldc.l @rm+,vbr 0100mmmm00100111 (rm) ? vbr, rm + 4 ? rm 3 ? lds rm,mach 0100mmmm00001010 rm ? mach 1 ? lds rm,macl 0100mmmm00011010 rm ? macl 1 ? lds rm,pr 0100mmmm00101010 rm ? pr 1 ? lds.l @rm+,mach 0100mmmm00000110 (rm) ? mach, rm + 4 ? rm 1 ? lds.l @rm+,macl 0100mmmm00010110 (rm) ? macl, rm + 4 ? rm 1 ? lds.l @rm+,pr 0100mmmm00100110 (rm) ? pr, rm + 4 ? rm 1 ? nop 0000000000001001 no operation 1 rte 0000000000101011 delayed branch, stack area ? pc/sr 4? sett 0000000000011000 1 ? t11 sleep 0000000000011011 sleep 3* stc sr,rn 0000nnnn00000010 sr ? rn 1 ? stc gbr,rn 0000nnnn00010010 gbr ? rn 1 ? stc vbr,rn 0000nnnn00100010 vbr ? rn 1 ? stc.l sr,@?n 0100nnnn00000011 rn? ? rn, sr ? (rn) 2 ? stc.l gbr,@?n 0100nnnn00010011 rn? ? rn, gbr ? (rn) 2 ? stc.l vbr,@?n 0100nnnn00100011 rn? ? rn, br ? (rn) 2 ? sts mach,rn 0000nnnn00001010 mach ? rn 1 ? sts macl,rn 0000nnnn00011010 macl ? rn 1 ? sts pr,rn 0000nnnn00101010 pr ? rn 1 ? 35 table 2.17 system control instructions (cont) instruction instruction code operation exec. cycles t bit sts.l mach,@?n 0100nnnn00000010 rn? ? rn, mach ? (rn) 1 ? sts.l macl,@?n 0100nnnn00010010 rn? ? rn, macl ? (rn) 1 ? sts.l pr,@?n 0100nnnn00100010 rn? ? rn, pr ? (rn) 1 ? trapa #imm 11000011iiiiiiii pc/sr ? stack area, (imm) ? pc 8? note: the number of execution cycles before the chip enters sleep mode. 36 2.5 processing states 2.5.1 state transitions the cpu has four processing states: reset, exception processing, program execution and power- down. figure 2.6 shows the transitions between the states. power-on reset state program execution state sleep mode exception processing state interrupt source occurs exception processing source occurs exception processing ends reset states power-down state res = 1 sleep instruction from only state when res = 0 figure 2.6 transitions between processing states reset state: the cpu resets in the reset state. when the res pin level goes low, a power-on reset results. exception processing state : the exception processing state is a transient state that occurs when exception processing sources such as resets or interrupts alter the cpu? processing state flow. 37 for a reset, the initial values of the program counter (pc) (execution start address) and stack pointer (sp) are fetched from the exception processing vector table and stored; the cpu then branches to the execution start address and execution of the program begins. for an interrupt, the stack pointer (sp) is accessed and the program counter (pc) and status register (sr) are saved to the stack area. the exception service routine start address is fetched from the exception processing vector table; the cpu then branches to that address and the program starts executing, thereby entering the program execution state. program execution state : in the program execution state, the cpu sequentially executes the program. power-down state : in the power-down state, the cpu operation halts and power consumption declines. the sleep instruction places the cpu in the power-down state. 39 section 3 power-down state 3.1 overview in the power-down state, cpu functions are halted, greatly reducing the power consumption of the chip. 3.1.1 power-down state the power-down state consists of a sleep mode. table 3.1 shows the conditions for entering sleep mode from the program execution state, the state of the cpu and on-chip peripheral functions in sleep mode, and the methods of exiting sleep mode. table 3.1 power-down state state mode entering conditions clock cpu on-chip peripheral modules cpu registers on-chip ram i/o ports exiting methods sleep execution of sleep instruction active halted active held held held 1. interrupt 2. power-on reset 40 3.2 sleep mode 3.2.1 transition to sleep mode when the sleep instruction is executed, the chip makes a transition from the program execution state to sleep mode. immediately after execution of the sleep instruction the cpu halts, but the contents of its internal registers are retained. on-chip peripheral modules continue to operate. 3.2.2 exit from sleep mode sleep mode is exited by an interrupt or a power-on reset. exit by interrupt: when an interrupt is generated, sleep mode is exited and interrupt exception processing is executed. if the priority level of the generated interrupt is not higher than the mask level set in the cpu? status register (sr), or if an interrupt by an on-chip peripheral module is disabled on the module side, the interrupt request will not be accepted and sleep mode will not be exited. exit by power-on reset: when the res pin is driven low, the chip exits sleep mode and enters the power-on reset state. 41 section 4 clock pulse generator (cpg) 4.1 overview the clock pulse generator (cpg) supplies clock pulses within the SH7011 and to external devices. the SH7011? cpg operates the SH7011 at a frequency equal to the oscillation frequency of the crystal resonator. the cpg is composed of an oscillator and a duty adjustment circuit (figure 4.1). there are two ways of generating a clock with the cpg: by connecting a crystal resonator, or by inputting an external clock. extal cpg xtal internal clock ( f ) oscillator duty adjustment circuit ck (system clock) figure 4.1 cpg block diagram 4.2 clock source either a crystal resonator or an external clock can be selected as the clock pulse source. 4.2.1 crystal resonator connection circuit configuration: figure 4.2 shows the method of connecting a crystal resonator. use the damping resistance (rd) shown in table 4.1. an at-cut parallel-resonance type crystal resonator with the same frequency as the system clock (ck) should be used. load capacitors (c l1 , c l2 ) must be connected as shown in the figure. the clock pulses generated by the crystal resonator and internal oscillator are sent to the duty adjustment circuit. after the duty has been adjusted, the pulses are supplied within the SH7011 chip and to external devices. 42 extal xtal cl1 cl2 rd cl1 = cl2 = t.b.d figure 4.2 example of crystal resonator connection table 4.1 damping resistance value frequency (mhz) 20 rd ( w ) t.b.d. crystal resonator: figure 4.3 shows an equivalent circuit for the crystal resonator. use a crystal resonator with the characteristics shown in table 4.2. xtal l cl co rs extal figure 4.3 crystal resonator equivalent circuit table 4.2 crystal resonator characteristics frequency (mhz) parameter 20 rs max ( w ) t.b.d. co max (pf) t.b.d. 43 4.2.2 external clock input input the external clock to the extal pin and leave the xtal pin open (figure 4.4.). the external clock frequency should be the same as that of the system clock (ck). xtal open extal external clock input figure 4.4 external clock input 4.3 usage notes note on board design: place the crystal resonator and load capacitors as close as possible to the extal and xtal pins. to prevent induction from interfering with correct oscillation, ensure that other signal lines to not cross the extal and xtal pin signal lines. xtal SH7011 extal avoid crossing signal lines c l2 c l1 figure 4.5 note on board design 44 notes on duty adjustment: duty adjustment circuit is performed on an input clock of 5 mhz or higher. with a frequency of less than 5 mhz, duty adjustment may not be performed, but ac characteristics t ch (clock high-level width) and t cl (clock low-level width) are satisfied, and there is no problem with SH7011 internal operation. figure 4.6 shows the basic characteristics of the duty adjustment circuit. the duty adjustment circuit does not correct for transient fluctuations or jitter in the input clock. thus, several tens of m s are required until duty adjustment is performed and a stable clock is obtained. 30 40 50 60 70 70 60 50 40 30 output duty (%) 15 input duty input frequency (mhz) 21020 figure 4.6 duty adjustment circuit characteristics 45 section 5 exception processing 5.1 overview 5.1.1 types of exception processing and priority exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 5.1. when several exception processing sources occur at once, they are processed according to the priority shown. table 5.1 types of exception processing and priority order exception source priority reset power-on reset high address error cpu address error interrupt nmi irq on-chip peripheral modules: multifunction timer/pulse unit (mtu) serial communications interface (sci) a/d converter (a/d) compare match timer (cmt) 8-bit timer 1 (tim1) 8-bit timer 2 (tim2) instructions trap instruction (trapa instruction) general illegal instructions (undefined code) illegal slot instructions (undefined code placed directly after a delay branch instruction* 1 or instructions that rewrite the pc* 2 ) low notes: 1. delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf. 2. instructions that rewrite the pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf. 46 5.1.2 exception processing operations the exception processing sources are detected and begin processing according to the timing shown in table 5.2. table 5.2 timing of exception source detection and the start of exception processing exception source timing of source detection and start of processing power-on reset starts when the res pin changes from low to high. address error detected when instruction is decoded and starts when the previous executing instruction finishes executing. interrupts detected when instruction is decoded and starts when the previous executing instruction finishes executing. instructions trap instruction starts from the execution of a trapa instruction. general illegal instructions starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). illegal slot instructions starts from the decoding of undefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the pc. when exception processing starts, the cpu operates as follows: 1. exception processing triggered by reset: the initial values of the program counter (pc) and stack pointer (sp) are fetched from the exception processing vector table (pc and sp are respectively the h'00000000 and h'00000004 addresses). see section 5.1.3, exception processing vector table, for more information. 0 is then written to the vector base register (vbr) and 1111 is written to the interrupt mask bits (i3ei0) of the status register (sr). the program begins running from the pc address fetched from the exception processing vector table. 2. exception processing triggered by address errors, interrupts and instructions: sr and pc are saved to the stack indicated by r15. for interrupt exception processing, the interrupt priority level is written to the sr?s interrupt mask bits (i3ei0). for address error and instruction exception processing, the i3ei0 bits are not affected. the start address is then fetched from the exception processing vector table and the program begins running from that address. 47 5.1.3 exception processing vector table before exception processing begins running, the exception processing vector table must be set in memory. the exception processing vector table stores the start addresses of exception service routines. (the reset exception processing table holds the initial values of pc and sp.) all exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. during exception processing, the start addresses of the exception service routines are fetched from the exception processing vector table, which indicated by this vector table address. table 5.3 shows the vector numbers and vector table address offsets. table 5.4 shows how vector table addresses are calculated. table 5.3 exception processing vector table exception sources vector numbers vector table address?ffset power-on reset pc 0 h'00000000?'00000003 sp 1 h'00000004?'00000007 (reserved by system) 2 h'00000008?'0000000f 3 general illegal instruction 4 h'00000010?'00000013 (reserved by system) 5 h'00000014?'00000017 slot illegal instruction 6 h'00000018?'0000001b (reserved by system) 7 h'0000001c?'0000001f (reserved by system) 8 h'00000020?'00000023 cpu address error 9 h'00000024?'00000027 (reserved by system) 10 h'00000028?'0000002b interrupts nmi 11 h'0000002c?'0000002f (reserved by system) 12 : 31 h'00000030?'00000033 : h'0000007c?'0000007f trap instruction (user vector) 32 : 63 h'00000080?'00000083 : h'000000fc?'000000ff 48 table 5.3 exception processing vector table (cont) exception sources vector numbers vector table address?ffset interrupts irq0 64 h'00000100?'00000103 irq1 65 h'00000104?'00000107 irq2 66 h'00000108?'0000010b irq3 67 h'0000010c?'0000010f irq4 68 h'00000110?'00000113 irq5 69 h'00000114?'00000117 irq6 70 h'00000118?'0000011b irq7 71 h'0000011c?'0000011f on-chip peripheral module* 72 : 255 h'00000120?'00000124 : h'000003fc?'000003ff note: the vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in section 6, interrupt controller, table 6.3, interrupt exception processing vectors and priorities. table 5.4 calculating exception processing vector table addresses exception source vector table address calculation resets vector table address = (vector table address offset) = (vector number) 4 address errors, interrupts, instructions vector table address = vbr + (vector table address offset) = vbr + (vector number) 4 notes: 1. vbr: vector base register 2. vector table address offset: see table 5.3. 3. vector number: see table 5.3. 49 5.2 resets 5.2.1 reset a reset has the highest priority of any exception source. as shown in table 5.5, a power-on reset initializes the internal state of the cpu and the on-chip peripheral module registers. table 5.5 types of resets conditions for transition to reset status internal status type res cpu on-chip peripheral module power-on reset low initialized initialized 5.2.2 power-on reset when the res pin is driven low, the lsi does a power-on reset. to reliably reset the lsi, the res pin should be kept at low for at least the duration of the oscillation settling time when applying power or when in standby mode (when the clock circuit is halted) or at least 20 t cyc (when the clock circuit is running). during power-on reset, cpu internal status and all registers of on-chip peripheral modules are initialized. see appendix b, pin status, for the status of individual pins during the power-on reset status. in the power-on reset status, power-on reset exception processing starts when the res pin is first driven low for a set period of time and then returned to high. the cpu will then operate as follows: 1. the initial value (execution start address) of the program counter (pc) is fetched from the exception processing vector table. 2. the initial value of the stack pointer (sp) is fetched from the exception processing vector table. 3. the vector base register (vbr) is cleared to h'00000000 and the interrupt mask bits (i3ei0) of the status register (sr) are set to h'f (1111). 4. the values fetched from the exception processing vector table are set in the program counter (pc) and sp and the program begins executing. be certain to always perform power-on reset processing when turning the system power on. 50 5.3 address errors address errors occur when instructions are fetched or data read or written, as shown in table 5.6. table 5.6 bus cycles and address errors bus cycle type bus cycle description address errors instruction fetch instruction fetched from even address none (normal) instruction fetched from odd address address error occurs instruction fetched from other than on-chip peripheral module space* none (normal) instruction fetched from on-chip peripheral module space* address error occurs data read/write word data accessed from even address none (normal) word data accessed from odd address address error occurs longword data accessed from other than a longword boundary address error occurs byte or word data accessed in on-chip peripheral module space* none (normal) longword data accessed in 16-bit on-chip peripheral module space* none (normal) longword data accessed in 8-bit on-chip peripheral module space* address error occurs note: see section 7, bus state controller. 5.3.1 address error exception processing when an address error occurs, the bus cycle in which the address error occurred ends. when the executing instruction then finishes, address error exception processing starts up. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the start address of the instruction to be executed after the last executed instruction. 3. the exception service routine start address is fetched from the exception processing vector table that corresponds to the address error that occurred and the program starts executing from that address. the jump that occurs is not a delayed branch. 51 5.4 interrupts table 5.7 shows the sources that start up interrupt exception processing. these are divided into nmi, irq and on-chip peripheral modules. table 5.7 interrupt sources type request source number of sources nmi nmi pin (external input) 1 irq irq0 e irq7 (external input) 8 on-chip peripheral module multifunction timer/pulse unit (mtu) 11 serial communications interface (sci) 4 a/d converter 1 compare match timer (cmt) 2 8-bit timer 1 1 8-bit timer 2 1 each interrupt source is allocated a different vector number and vector table offset. see section 6, interrupt controller, table 6.3, interrupt exception processing vectors and priorities, for more information on vector numbers and vector table address offsets. 5.4.1 interrupt priority level the interrupt priority order is predetermined. when multiple interrupts occur simultaneously (overlap), the interrupt controller (intc) determines their relative priorities and starts up processing according to the results. the priority order of interrupts is expressed as priority levels 0?6, with priority 0 the lowest and priority 16 the highest. the nmi interrupt has priority 16 and cannot be masked, so it is always accepted. the user break interrupt priority level is 15. irq interrupts and on-chip peripheral module interrupt priority levels can be set freely using the intc? interrupt priority level setting registers a through h (ipra to iprh) as shown in table 5.8. the priority levels that can be set are 0?5. level 16 cannot be set. see section 6.3.1, interrupt priority registers a-h (ipra-iprh), for more information on ipra to iprh. 52 table 5.8 interrupt priority order type priority level comment nmi 16 fixed priority level. cannot be masked. irq 0?5 set with interrupt priority level setting registers a through h (ipra to iprh). on-chip peripheral module 0?5 set with interrupt priority level setting registers a through h (ipra to iprh). 5.4.2 interrupt exception processing when an interrupt occurs, its priority level is ascertained by the interrupt controller (intc). nmi is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (i3?0) of the status register (sr). when an interrupt is accepted, exception processing begins. in interrupt exception processing, the cpu saves sr and the program counter (pc) to the stack. the priority level value of the accepted interrupt is written to sr bits i3?0. for nmi, however, the priority level is 16, but the value set in i3?0 is h'f (level 15). next, the start address of the exception service routine is fetched from the exception processing vector table for the accepted interrupt, that address is jumped to and execution begins. see section 6.4, interrupt operation, for more information on the interrupt exception processing. 5.5 exceptions triggered by instructions exception processing can be triggered by trap instructions, general illegal instructions, and illegal slot instructions, as shown in table 5.9. table 5.9 types of exceptions triggered by instructions type source instruction comment trap instructions trapa illegal slot instructions undefined code placed immediately after a delayed branch instruction (delay slot) and instructions that rewrite the pc delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf instructions that rewrite the pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf general illegal instructions undefined code anywhere besides in a delay slot 53 5.5.1 trap instructions when a trapa instruction is executed, trap instruction exception processing starts up. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the start address of the instruction to be executed after the trapa instruction. 3. the exception service routine start address is fetched from the exception processing vector table that corresponds to the vector number specified in the trapa instruction. that address is jumped to and the program starts executing. the jump that occurs is not a delayed branch. 5.5.2 illegal slot instructions an instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. when the instruction placed in the delay slot is undefined code, illegal slot exception processing starts up when that undefined code is decoded. illegal slot exception processing also starts up when an instruction that rewrites the program counter (pc) is placed in a delay slot. the processing starts when the instruction is decoded. the cpu handles an illegal slot instruction as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the jump address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the pc. 3. the exception service routine start address is fetched from the exception processing vector table that corresponds to the exception that occurred. that address is jumped to and the program starts executing. the jump that occurs is not a delayed branch. 5.5.3 general illegal instructions when undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. the cpu handles general illegal instructions the same as illegal slot instructions. unlike processing of illegal slot instructions, however, the program counter value stored is the start address of the undefined code. 54 5.6 when exception sources are not accepted when an address error or interrupt is generated after a delayed branch instruction or interrupt- disabled instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.10. when this happens, it will be accepted when an instruction that can accept the exception is decoded. table 5.10 generation of exception sources immediately after a delayed branch instruction or interrupt-disabled instruction exception source point of occurrence address error interrupt immediately after a delayed branch instruction *1 not accepted not accepted immediately after an interrupt-disabled instruction *2 accepted not accepted notes: 1. delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf 2. interrupt-disabled instructions: ldc, ldc.l, stc, stc.l, lds, lds.l, sts, sts.l 5.6.1 immediately after a delayed branch instruction when an instruction placed immediately after a delayed branch instruction (delay slot) is decoded, neither address errors nor interrupts are accepted. the delayed branch instruction and the instruction located immediately after it (delay slot) are always executed consecutively, so no exception processing occurs during this period. 5.6.2 immediately after an interrupt-disabled instruction when an instruction immediately following an interrupt-disabled instruction is decoded, interrupts are not accepted. address errors are accepted. 55 5.7 stack status after exception processing ends the status of the stack after exception processing ends is as shown in table 5.11. table 5.11 types of stack status after exception processing ends types stack status address error 32 bits 32 bits sr address of instruction after executed instruction sp trap instruction 32 bits 32 bits sr address of instruction after trapa instruction sp general illegal instruction 32 bits 32 bits sr start address of illegal instruction sp interrupt 32 bits 32 bits sr address of instruction after executed instruction sp illegal slot instruction 32 bits 32 bits sr jump destination address of delay branch instruction sp 56 5.8 notes on use 5.8.1 value of stack pointer (sp) the value of the stack pointer must always be a multiple of four. if it is not, an address error will occur when the stack is accessed during exception processing. 5.8.2 value of vector base register (vbr) the value of the vector base register must always be a multiple of four. if it is not, an address error will occur when the stack is accessed during exception processing. 5.8.3 address errors caused by stacking of address error exception processing when the stack pointer is not a multiple of four, an address error will occur during stacking of the exception processing (interrupts, etc.) and address error exception processing will start up as soon as the first exception processing is ended. address errors will then also occur in the stacking for this address error exception processing. to ensure that address error exception processing does not go into an endless loop, no address errors are accepted at that point. this allows program control to be shifted to the address error exception service routine and enables error processing. when an address error occurs during exception processing stacking, the stacking bus cycle (write) is executed. during stacking of the status register (sr) and program counter (pc), the sp is ? for both, so the value of sp will not be a multiple of four after the stacking either. the address value output during stacking is the sp value, so the address where the error occurred is itself output. this means the write data stacked will be undefined. 57 section 6 interrupt controller (intc) 6.1 overview the interrupt controller (intc) ascertains the priority of interrupt sources and controls interrupt requests to the cpu. the intc has registers for setting the priority of each interrupt which can be used by the user to order the priorities in which the interrupt requests are processed. 6.1.1 features the intc has the following features: 16 levels of interrupt priority: by setting the eight interrupt-priority level registers, the priorities of irq interrupts and on-chip peripheral module interrupts can be set in 16 levels for different request sources. nmi noise canceler function: nmi input level bits indicate the nmi pin status. by reading these bits with the interrupt exception service routine, the pin status can be confirmed, enabling it to be used as a noise canceler. 58 6.1.2 block diagram figure 6.1 is a block diagram of the intc. cpu sr interrupt request com- parator priority ranking judg- ment input control (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) isr icr ipr ipra?prh module bus bus interface internal bus i3 i2 i1 i0 intc nmi irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 mtu cmt sci a/d tim1 (interrupt request) tim2 mtu: cmt: sci: a/d: tim: multifunction timer pulse unit compare match timer serial communication interface a/d converter 8-bit timer icr: isr: ipraeiprh: sr: interrupt control register irq ststus register interrupt priority level setting registers a to h status register figure 6.1 intc block diagram 59 6.1.3 pin configuration table 6.1 shows the intc pin configuration. table 6.1 pin configuration name abbreviation i/o function non-maskable interrupt input pin nmi i input of non-maskable interrupt request signal interrupt request input pins irq0 e irq7 i input of maskable interrupt request signals 6.1.4 register configuration the intc has the 10 registers shown in table 6.2. these registers set the priority of the interrupts and control external interrupt input signal detection. table 6.2 register configuration name abbr. r/w initial value address access sizes interrupt priority register a ipra r/w h'0000 h'ffff8348 8, 16, 32 interrupt priority register b iprb r/w h'0000 h'ffff834a 8, 16, 32 interrupt priority register c iprc r/w h'0000 h'ffff834c 8, 16, 32 interrupt priority register d iprd r/w h'0000 h'ffff834e 8, 16, 32 interrupt priority register e ipre r/w h'0000 h'ffff8350 8, 16, 32 interrupt priority register f iprf r/w h'0000 h'ffff8352 8, 16, 32 interrupt priority register g iprg r/w h'0000 h'ffff8354 8, 16, 32 interrupt priority register h iprh r/w h'0000 h'ffff8356 8, 16, 32 interrupt control register icr r/w * 1 h'ffff8358 8, 16, 32 irq status register isr r(w) * 2 h'0000 h'ffff835a 8, 16, 32 notes: 1. the value when the nmi pin is high is h'8000; when the nmi pin is low, it is h'0000. 2. only 0 can be written, in order to clear flags. 60 6.2 interrupt sources there are four types of interrupt sources: nmi, user breaks, irq, and on-chip peripheral modules. each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). giving an interrupt a priority level of 0 masks it. 6.2.1 nmi interrupts the nmi interrupt has priority 16 and is always accepted. input at the nmi pin is detected by edge. use the nmi edge select bit (nmie) in the interrupt control register (icr) to select either the rising or falling edge. nmi interrupt exception processing sets the interrupt mask level bits (i3?0) in the status register (sr) to level 15. 6.2.2 irq interrupts irq interrupts are requested by input from pins irq0 e irq7 . set the irq sense select bits (irq0seirq7s) of the interrupt control register (icr) to select low level detection or falling edge detection for each pin. the priority level can be set from 0 to 15 for each pin using the interrupt priority registers a and b (ipraeiprb). when irq interrupts are set to low level detection, an interrupt request signal is sent to the intc during the period the irq pin is low level. interrupt request signals are not sent to the intc when the irq pin becomes high level. interrupt request levels can be confirmed by reading the irq flags (irq0feirq7f) of the irq status register (isr). when irq interrupts are set to falling edge detection, interrupt request signals are sent to the intc upon detecting a change on the irq pin from high to low level. irq interrupt request detection results are maintained until the interrupt request is accepted. confirmation that irq interrupt requests have been detected is possible by reading the irq flags (irq0feirq7f) of the irq status register (isr), and by writing a 0 after reading a 1, irq interrupt request detection results can be withdrawn. in irq interrupt exception processing, the interrupt mask bits (i3ei0) of the status register (sr) are set to the priority level value of the accepted irq interrupt. 61 6.2.3 on-chip peripheral module interrupts on-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules: multifunction timer pulse unit (mtu) compare match timer (cmt) serial communications interface (sci) a/d converter (a/d) 8-bit timer 1 (tim1) 8-bit timer 2 (tim2) a different interrupt vector is assigned to each interrupt source, so the exception service routine does not have to decide which interrupt has occurred. priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers ceh (iprce iprh). on-chip peripheral module interrupt exception processing sets the interrupt mask level bits (i3ei0) in the status register (sr) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.2.4 interrupt exception vectors and priority rankings table 6.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. each interrupt source is allocated a different vector number and vector table address offset. vector table addresses are calculated from vector numbers and address offsets. in interrupt exception processing, the exception service routine start address is fetched from the vector table indicated by the vector table address. see section 5 exception processing, table 5.4, calculating exception processing vector table addresses. irq interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers a? (ipra?prh). the ranking of interrupt sources for iprc?prh, however, must be the order listed under priority order within ipr setting range in table 6.3 and cannot be changed. a power-on reset assigns priority level 0 to irq interrupts and on-chip peripheral module interrupts. if the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 6.3. 62 table 6.3 interrupt exception processing vectors and priorities interrupt vector interrupt priority interrupt source vector no. vector table address offset priority (initial value) corre- sponding ipr (bits) within ipr setting range default priority nmi 11 h'0000002c to h'0000002f 16 high irq0 64 h'00000100 to h'00000103 0 to 15 (0) ipra (15?2) irq1 65 h'00000104 to h'00000107 0 to 15 (0) ipra (11?) irq2 66 h'00000108 to h'0000010b 0 to 15 (0) ipra (7?) irq3 67 h'0000010c to h'0000010f 0 to 15 (0) ipra (3?) irq4 68 h'00000110 to h'00000113 0 to 15 (0) iprb (15?2) irq5 69 h'00000114 to h'00000117 0 to 15 (0) iprb (11?) irq6 70 h'00000118 to h'0000011b 0 to 15 (0) iprb (7?) irq7 71 h'0000011c to h'0000011f 0 to 15 (0) iprb (3?) mtu0 tgi0a 88 h'00000160 to h'00000163 0 to 15 (0) iprd (15?2) high tgi0b 89 h'00000164 to h'00000167 0 to 15 (0) tgi0c 90 h'00000168 to h'0000016b 0 to 15 (0) tgi0d 91 h'0000016c to h'0000016f 0 to 15 (0) low tci0v 92 h'00000170 to h'00000173 0 to 15 (0) iprd (11?) low 63 table 6.3 interrupt exception processing vectors and priorities (cont) interrupt vector interrupt priority interrupt source vector no. vector table address offset priority (initial value) corre- sponding ipr (bits) within ipr setting range default priority mtu1 tgi1a 96 h'00000180 to h'00000183 0 to 15 (0) iprd (7?) high high tgi1b 97 h'00000184 to h'00000187 0 to 15 (0) low tci1v 100 h'00000190 to h'00000193 0 to 15 (0) iprd (3?) mtu2 tgi2a 104 h'000001a0 to h'000001a3 0 to 15 (0) ipre (15?2) high tgi2b 105 h'000001a4 to h'000001a7 0 to 15 (0) low tci2v 108 h'000001b0 to h'000001b3 0 to 15 (0) ipre (11?) sci eri 132 h'00000210 to h'00000213 0 to 15 (0) iprf (3?) high rxi 133 h'00000214 to h'00000217 txi 134 h'00000218 to h'0000021b tei 135 h'0000021c to h'0000021f low a/d adi 138 h'00000228 to h'0000022b 0 to 15 (0) iprg (15?2) cmt0 cmi0 144 h'00000240 to h'00000243 0 to 15 (0) iprg (7?) cmt1 cmi1 148 h'00000250 to h'00000253 0 to 15 (0) iprg (3?) tim1 iti 152 h'00000260 to h'00000263 0 to 15 (0) iprh (15?2) high tim2 cmi 153 h'00000264 to h'00000267 low low 64 6.3 description of registers 6.3.1 interrupt priority registers a? (ipra?prh) interrupt priority registers a? (ipra?prh) are 16-bit readable/writable registers that set priority levels from 0 to 15 for irq interrupts and on-chip peripheral module interrupts. correspondence between interrupt request sources and each of the ipra?prh bits is shown in table 6.4. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 6.4 interrupt request sources and ipra?prh bits register 15?2 11? 7? 3? interrupt priority register a irq0 irq1 irq2 irq3 interrupt priority register b irq4 irq5 irq6 irq7 interrupt priority register c reserved reserved reserved reserved interrupt priority register d mtu0 mtu0 mtu1 mtu1 interrupt priority register e mtu2 mttu2 reserved reserved interrupt priority register f reserved reserved reserved sci interrupt priority register g a/d reserved cmt0 cmt1 interrupt priority register h tim1, 2 reserved reserved reserved as indicated in table 6.4, four irq pins or groups of 4 on-chip peripheral modules are allocated to each register. each of the corresponding interrupt priority ranks are established by setting a value from h'0 (0000) to h'f (1111) in each of the four-bit groups 15e12, 11e8, 7e4 and 3e0. interrupt priority rank becomes level 0 (lowest) by setting h'0, and level 15 (highest) by setting h'f. 8-bit timers 1 and 2 are set to the same priority rank. 65 ipraeiprh are initialized to h'0000 by a power-on reset. reserved bits always return 0 if read, and the write value for these bits should always be 0. 6.3.2 interrupt control register (icr) the icr is a 16-bit register that sets the input signal detection mode of the external interrupt input pin nmi and irq0 e irq7 and indicates the input signal level to the nmi pin. a power-on reset initializes icr. bit: 15 14 13 12 11 10 9 8 nmil ? ? ? ? ? ? nmie initial value: * 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bit: 7 6 5 4 3 2 1 0 irq0s irq1s irq2s irq3s irq4s irq5s irq6s irq7s initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: when nmi input is high: 1; when nmi input is low: 0 bit 15?nmi input level (nmil): sets the level of the signal input at the nmi pin. this bit can be read to determine the nmi pin level. this bit cannot be modified. bit 15: nmil description 0 nmi input level is low 1 nmi input level is high bits 14 to 9?reserved: these bits always read as 0. the write value should always be 0. bit 8?nmi edge select (nmie) bit 8: nmie description 0 interrupt request is detected on falling edge of nmi input (initial value) 1 interrupt request is detected on rising edge of nmi input 66 bits 7 to 0?irq0eirq7 sense select (irq0seirq7s): these bits set the irq0eirq7 interrupt request detection mode. bits 7-0: irq0s?rq7s description 0 interrupt request is detected on low level of irq input (initial value) 1 interrupt request is detected on falling edge of irq input 6.3.3 irq status register (isr) the isr is a 16-bit register that indicates the interrupt request status of the external interrupt input pins irq0 e irq7 . when irq interrupts are set to edge detection, held interrupt requests can be withdrawn by writing a 0 to irqnf after reading an irqnf = 1. a power-on reset initializes isr. bit: 15 14 13 12 11 10 9 8 ???????? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 irq0f irq1f irq2f irq3f irq4f irq5f irq6f irq7f initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 8?reserved: these bits always read as 0. the write value should always be 0. 67 bits 7 to 0?irq0eirq7 flags (irq0feirq7f): these bits display the irq0eirq7 interrupt request status. bits 7-0: irq0f?rq7f detection setting description 0 level detection no irqn interrupt request exists. clear conditions: when irqn input is high level edge detection no irqn interrupt request was detected. (initial value) clear conditions: 1. when a 0 is written after reading irqnf = 1 status 2. when irqn interrupt exception processing has been executed 1 level detection an irqn interrupt request exists. set conditions: when irqn input is low level edge detection an irqn interrupt request was detected. set conditions: when a falling edge occurs at an irqn input irq pin edge detection selection cpu interrupt request (irqn interrupt acceptance/irqnf = 0 write after irqnf = 1 read) s r resirqn q irqns (0: level, 1: edge) isr.irqnf level detection figure 6.2 external interrupt process 68 6.4 interrupt operation 6.4.1 interrupt sequence the sequence of interrupt operations is explained below. figure 6.3 is a flowchart of the operations. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest priority interrupt in the interrupt requests sent, following the priority levels set in interrupt priority level setting registers a? (ipra?prh). lower-priority interrupts are ignored*. if a number of interrupts with the same priority level occur, or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its ipr setting range (as indicated in table 6.3) is selected. 3. the interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (i3?0) in the cpu? status register (sr). if the request priority level is equal to or less than the level set in i3?0, the request is ignored. if the request priority level is higher than the level in bits i3?0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the cpu. 4. the interrupt controller detects the interrupt request sent from the interrupt controller when it decodes the next instruction to be executed. instead of executing the decoded instruction, the cpu starts interrupt exception processing (figure 6.4). 5. the status register (sr) and program counter (pc) are saved onto the stack. 6. the priority level of the accepted interrupt is written to bits i3?0 in sr. 7. the cpu reads the start address of the exception service routine from the exception vector table for the accepted interrupt, jumps to that address, and starts executing the program there. this jump is not a delay branch. note: an interrupt request for which edge detection has been set is held pending until it is accepted. however, an irq interrupt can be cleared by an irq status register (isr) access. for details see section 6.2.3, irq interrupts. pending edge-detected interrupts are cleared by a power-on reset. 69 no yes nmi? no yes level 15 interrupt? no yes i3 to i0 level 14? no yes level 14 interrupt? no yes yes i3 to i0 level 13? no yes level 1 interrupt? no yes i3 to i0 = level 0? no program execution state save sr to stack save pc to stack branches to exception service routine i3 to i0: interrupt mask bits of status register interrupt? copy accept-interrupt level to i3 to i0 reads exception vector table figure 6.3 interrupt sequence flowchart 70 6.4.2 stack after interrupt exception processing figure 6.4 shows the stack after interrupt exception processing. 32 bits 32 bits pc* 1 sr address 4n? 4n? 4n sp* 2 notes: 1. 2. pc: start address of the next instruction (return destination instruction) after the executing instruction always be certain that sp is a multiple of 4 figure 6.4 stack after interrupt exception processing 6.5 interrupt response time table 6.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. figure 6.5 shows the pipeline when an irq interrupt is accepted. 71 table 6.5 interrupt response time number of states item nmi, peripheral module irq notes compare identified inter- rupt priority with sr mask level 2 or 3 4 wait for completion of sequence currently being executed by cpu x ( 3 0) the longest sequence is for interrupt or address-error exception processing (x = 4 + m1 + m2 + m3 + m4). if an interrupt-masking instruction follows, however, the time may be even longer. time from start of interrupt exception processing until fetch of first instruction of exception service routine starts 5 + m1 + m2 + m3 performs the pc and sr saves and vector address fetch. interrupt total: 7 + m1 + m2 + m3 9 + m1 + m2 + m3 response minimum: 10 12 time maximum: 12 + 2 (m1 + m2 + m3) + m4 13 + 2 (m1 + m2 + m3) + m4 note: when m1 = m2 = m3 = m4 = 1 m1em4 are the number of states needed for the following memory accesses. m1: sr save (longword write) m2: pc save (longword write) m3: vector address read (longword read) m4: fetch first instruction of interrupt service routine response minimum 7 + m1 + m2 + m3 9 + m1 + m2 + m3 time 0.5 m s* 0.6 m s* maximum 12 + 2 (m1 + m2 + m3) + m4 13 + 2 (m1 + m2 + m3) + m4 0.95 m s* 1.0 m s* note: 20 mhz operation, m1 = m2 = m3 = m4 = 1 72 fde mee mme ee fd f 4 3 interrupt acceptance irq m1 m2 1 m3 1 5 + m1 + m2 + m3 instruction (instruction replaced by interrupt exception processing) overrun fetch interrupt service routine start instruction f: d: e: m: instruction fetch (instruction fetched from memory where program is stored). instruction decoding (fetched instruction is decoded). instruction execution (data operation and address calculation is performed according to the results of decoding). memory access (data in memory is accessed). figure 6.5 pipeline when an irq interrupt is accepted 73 section 7 bus state controller (bsc) 7.1 overview the bus state controller (bsc) divides up the address spaces and outputs control for various types of memory. this enables memories like sram, and rom to be linked directly to the lsi without external circuitry. 7.1.1 features address space is divided into four spaces ? a maximum linear 4 mbytes for each of address spaces cs0-cs3 ? 16-bit bus width ? wait states can be inserted by software for each space (0-3 waits) ? in external memory space access, wait states can be inserted by the wait pin ? outputs control signals for each space according to the type of memory connected ram interface ? on-chip ram access of 32 bits in 1 state 74 7.1.2 block diagram figure 7.1 shows the bsc block diagram. bus interface wcr1 bcr2 internal bus wait control unit wait area control unit cs0 e cs3 rd memory control unit wrh , wrl module bus bsc wcr1: bcr2: wait control register 1 bus control register 2 figure 7.1 bsc block diagram 75 7.1.3 pin configuration table 7.1 shows the bus state controller pin configuration. table 7.1 pin configuration pin name i/o function a21?1 output address output d15?0 i/o 16-bit data bus cs0 e cs3 output chip select rd output strobe that indicates a read cycle for ordinary space/multiplex i/o wrh output strobe that indicates an upper byte (d15ed8) write cycle wrl output strobe that indicates a lower byte (d7ed0) write cycle wait input wait state request signal 7.1.4 register configuration the bus state controller has two registers. the functions of these registers include control of wait states and interfaces with memories such as rom and sram. the registers are summarized in figure table 7.2. both registers are 16 bits in size, and are initialized by a power-on reset. table 7.2 register configuration name abbr. r/w initial value address access size bus control register 2 bcr2 r/w h'ffff h'ffff8622 8, 16 wait state control register 1 wcr1 r/w h'ffff h'ffff8624 8, 16 76 7.1.5 address map figure 7.2 shows the address format used by the sh7092. a31?24 a23, a22 a21 a1 output address: output from the address pins space selection: not output externally; used to select the type of space reserved (do not access) when 00000010 to 11111110 (h'01 to h'fe) on-chip peripheral module space or on-chip ram space when 11111111 (h'ff) cs space selection: decoded, outputs cs0 to cs3 when a31 to a24 = 00000000 a0 figure 7.2 address format this lsi uses 32-bit addresses: a31 to a24 are used to select the type of space and are not output externally. bits a23 and a22 are decoded and output as chip select signals ( cs0 to cs3 ) for the corresponding areas when bits a31 to a24 are 00000000. a21 to a1 are output externally. table 7.3 shows an address map. table 7.3 address map address space memory size bus width h'00200000 to h'003fffff cs0 space ordinary space 4 mbytes 16 bits h'00400000 to h'007fffff cs1 space ordinary space 4 mbytes 16 bits h'00800000 to h'00bfffff cs2 space ordinary space 4 mbytes 16 bits h'00c00000 to h'00ffffff cs3 space ordinary space 4 mbytes 16 bits h'01000000 to h'ffff7fff reserved reserved h'ffff8000 to h'ffff87ff on-chip peripheral module on-chip peripheral module 2 kbytes 8/16 bits h'ffff8800 to h'ffffe7ff reserved reserved h'ffffe800 to h'ffffffff on-chip ram on-chip ram 6 kbytes 32 bits note: do not access reserved spaces. operation cannot be guaranteed if they are accessed. 77 7.2 description of registers 7.2.1 bus control register 2 (bcr2) bcr2 is a 16-bit read/write register that specifies the number of idle cycles and cs signal assert extension of each cs space. bcr2 is initialized by power-on resets to h'ffff. bit: 15 14 13 12 11 10 9 8 iw31 iw30 iw21 iw20 iw11 iw10 iw01 iw00 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 cw3 cw2 cw1 cw0 sw3 sw2 sw1 sw0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15e8?idles between cycles (iw31, iw30, iw21, iw20, iw11, iw10, iw01, iw00): these bits specify idle cycles inserted between consecutive accesses when the second one is to a different cs area after a read. idles are used to prevent data conflict between rom (and other memories, which are slow to turn the read data buffer off), fast memories, and i/o interfaces. even when access is to the same area, idle cycles must be inserted when a read access is followed immediately by a write access. the idle cycles to be inserted comply with the area specification of the previous access . refer to section 7.4, waits between access cycles, for details. iw31, iw30 specify the idle between cycles for cs3 space; iw21, iw20 specify the idle between cycles for cs2 space; iw11, iw10 specify the idle between cycles for cs1 space and iw01, iw00 specify the idle between cycles for cs0 space. bit 15 (iw31) bit 14 (iw30) description 0 0 no idle cycle after accessing cs3 space 1 inserts one idle cycle 1 0 inserts two idle cycles 1 inserts three idle cycles ( initial value) 78 bit 13 (iw21) bit 12 (iw20) description 0 0 no idle cycle after accessing cs2 space 1 inserts one idle cycle 1 0 inserts two idle cycles 1 inserts three idle cycles ( initial value) bit 11 (iw11) bit 10 (iw10) description 0 0 no idle cycle after accessing cs1 space 1 inserts one idle cycle 1 0 inserts two idle cycles 1 inserts three idle cycles ( initial value) bit 9 (iw01) bit 8 (iw00) description 0 0 no idle cycle after accessing cs0 space 1 inserts one idle cycle 1 0 inserts two idle cycles 1 inserts three idle cycles ( initial value) bits 7e4?idle specification for continuous access (cw3, cw2, cw1, cw0): the continuous access idle specification makes insertions to clearly delineate the bus intervals by once negating the csn signal when doing consecutive accesses of the same cs space. when a write immediately follows a read, the number of idle cycles inserted is the larger of the two values specified by iw and cw. refer to section 7.6, waits between access cycles, for details. cw3 specifies the continuous access idles for cs3 space; cw2 specifies the continuous access idles for cs2 space; cw1 specifies the continuous access idles for cs1 space and cw0 specifies the continuous access idles for cs0 space. bit 7 (cw3) description 0 no cs3 space continuous access idle cycles 1 one cs3 space continuous access idle cycle (initial value) bit 6 (cw2) description 0 no cs2 space continuous access idle cycles 1 one cs2 space continuous access idle cycle (initial value) 79 bit 5 (cw1) description 0 no cs1 space continuous access idle cycles 1 one cs1 space continuous access idle cycle (initial value) bit 4 (cw0) description 0 no cs0 space continuous access idle cycles 1 one cs0 space continuous access idle cycle (initial value) bits 3e0? cs assert extension specification (sw3, sw2, sw1, sw0): the cs assert cycle extension specification is for making insertions to prevent extension of the rd signal or wrx signal assert period beyond the length of the csn signal assert period. extended cycles insert one cycle before and after each bus cycle, which simplifies interfaces with external devices and also has the effect of extending write data hold time. refer to section 7.3.3, cs assert extension function, for details. sw3 specifies the cs assert extension for cs3 space access; sw2 specifies the cs assert extension for cs2 space access; sw1 specifies the cs assert extension for cs1 space access and sw0 specifies the cs assert extension for cs0 space access. bit 3 (sw3) description 0 no cs3 space cs assert extension 1 cs3 space cs assert extension (initial value) bit 2 (sw2) description 0 no cs2 space cs assert extension 1 cs2 space cs assert extension (initial value) bit 1 (sw1) description 0 no cs1 space cs assert extension 1 cs1 space cs assert extension (initial value) bit 0 (sw0) description 0 no cs0 space cs assert extension 1 cs0 space cs assert extension (initial value) 80 7.2.2 wait control register 1 (wcr1) wait control register 1 (wcr1) is a 16-bit read/write register that specifies the number of wait cycles (0-3) for each cs space. wcr1 is initialized to h'ffff by power-on resets. bit: 15 14 13 12 11 10 9 8 w31 w30 w21 w20 initial value: 1 1 1 1 1 1 1 1 r/w: r r r/w r/w r r r/w r/w bit: 7 6 5 4 3 2 1 0 w11 w10 w01 w00 initial value: 1 1 1 1 1 1 1 1 r/w: r r r/w r/w r r r/w r/w bits 15 and 14?reserved. these bits always read 1. the write value should always be 1. bits 13 and 12?cs3 space wait specification (w31, w30): these bits specify the number of waits for cs3 space accesses. bit 13 (w31) bit 12 (w30) description 0 0 no wait (external wait input disabled) 1 1-wait external wait input enabled 1 0 2-wait external wait input enabled 1 3-wait external wait input enabled (initial value) bits 11 and 10?reserved. these bits always read 1. the write value should always be 1. bits 9 and 8?cs2 space wait specification (w21, w20): these bits specify the number of waits for cs2 space accesses. bit 9 (w21) bit 8 (w20) description 0 0 no wait (external wait input disabled) 1 1-wait external wait input enabled 1 0 2-wait external wait input enabled 1 3-wait external wait input enabled (initial value) 81 bits 7 and 6?reserved. these bits always read 1. the write value should always be 1. bits 5 and 4?cs1 space wait specification (w11, w10): these bits specify the number of waits for cs1 space accesses. bit 5 (w11) bit 4 (w10) description 0 0 no wait (external wait input disabled) 1 1-wait external wait input enabled 1 0 2-wait external wait input enabled 1 3-wait external wait input enabled (initial value) bits 3 and 2?reserved. these bits always read 1. the write value should always be 1. bits 1 and 0?cs0 space wait specification (w01, w00): these bits specify the number of waits for cs0 space accesses. bit 1 (w01) bit 0 (w00) description 0 0 no wait (external wait input disabled) 1 1-wait external wait input enabled 1 0 2-wait external wait input enabled 1 3-wait external wait input enabled (initial value) 82 7.3 accessing ordinary space a strobe signal is output by ordinary space accesses to provide primarily for sram or rom direct connections. 7.3.1 basic timing figure 7.3 shows the basic timing of ordinary space accesses. ordinary access bus cycles are performed in 2 states. t 1 ck address csn rd read write data wrx data t 2 figure 7.3 basic timing of ordinary space access during a read, irrespective of operand size, all bits in the data bus width for the access space (address) are fetched by the lsi on rd , using the required byte locations. during a write, the following signals are associated with transfer of these actual byte locations: wrh (bits 15e8) and wrl (bits 7e0). 83 7.3.2 wait state control the number of wait states inserted into ordinary space access states can be controlled using the wcr settings. the specified number of t w cycles (0? waits) are inserted as software wait cycles with the timing shown in figure 7.4. t 1 t w ck read write address csn rd data wrx data t 2 figure 7.4 wait timing of ordinary space access (software wait only) 84 when the wait is specified by software using wcr, the wait input wait signal from outside is sampled. figure 7.5 shows the wait signal sampling. the wait signal is sampled at the clock rise one cycle before the clock rise when t w state shifts to t 2 state. t 1 t w ck read write address csn wait rd data wrx data t w t w 0 t 2 figure 7.5 wait state timing of ordinary space access (wait states from software wait 2 state + wait signal) 85 7.3.3 cs assert period extension idle cycles can be inserted to prevent extension of the rd signal or wrx signal assert period beyond the length of the csn signal assert period by setting the sw3esw0 bits of bcr2. this allows for flexible interfaces with external circuitry. the timing is shown in figure 7.6. t h and t f cycles are added respectively before and after the ordinary cycle. only csn is asserted in these cycles; rd and wrx signals are not. further, data is extended up to the t f cycle, which is effective for gate arrays and the like, which have slower write operations. t h t 1 ck read write address csn rd data wrx data t 2 t f figure 7.6 cs assert period extension function 86 7.4 waits between access cycles when a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next access. if there is a data conflict during memory access, the problem can be solved by inserting a wait in the access cycle. to enable detection of bus cycle starts, waits can be inserted between access cycles during continuous accesses of the same cs space by negating the csn signal once. 7.4.1 prevention of data bus conflicts for the two cases of write cycles after read cycles, and read cycles for a different area after read cycles, waits are inserted so that the number of idle cycles specified by the iw31 to iw00 bits of the bcr2. when idle cycles already exist between access cycles, only the number of empty cycles remaining beyond the specified number of idle cycles are inserted. figure 7.7 shows an example of idles between cycles. in this example, 1 idle between csn space cycles has been specified, so when a csm space write immediately follows a csn space read cycle, 1 idle cycle is inserted. ck csn csm rd data csn space read csm space write idle cycle wrx address t 1 t 2 t 1 t 2 t idle figure 7.7 idle cycle insertion example 87 iw31 and iw30 specify the number of idle cycles required after a cs3 space read either to read other external spaces, or for this lsi, to do write accesses. in the same manner, iw21 and iw20 specify the number of idle cycles after a cs2 space read, iw11 and iw10, the number after a cs1 space read, and iw01 and iw00, the number after a cs0 space read. 0 to 3 cycles can be specified for cs space. 7.4.2 simplification of bus cycle start detection for consecutive accesses of the same cs space, waits are inserted so that the number of idle cycles designated by the cw3 to cw0 bits of the bcr2 occur. however, for write cycles after reads, the number of idle cycles inserted will be the larger of the two values defined by the iw and cw bits. when idle cycles already exist between access cycles, waits are not inserted. figure 7.8 shows an example. a continuous access idle is specified for csn space, and csn space is consecutively write accessed. ck csn rd wrx data csn space access csn space access idle cycle address t 1 t 2 t 1 t 2 t idle figure 7.8 same space consecutive access idle cycle insertion example 88 7.5 memory connection examples SH7011 256k 16 bits rom ce oe csn rd a1ea18 d0ed15 a0ea17 i/o0ei/o15 figure 7.9 16-bit data bus width rom connection SH7011 128k 8 bits sram csn rd cs oe a1ea17 a0ea16 wrh we d8ed15 i / o0ei/o7 wrl d0ed7 cs oe a0ea16 we i / o0ei/o7 figure 7.10 16-bit data bus width sram connection 89 section 8 multifunction timer pulse unit (mtu) 8.1 overview the sh microprocessor has an on-chip 16-bit multifunction timer pulse unit (mtu) with three channels of 16-bit timers. 8.1.1 features ? can process a maximum of six different pulse outputs and inputs. ? has eight timer general registers (tgr), four for channel 0 and two each for channels 1 and 2, that can be set to function independently as output compare registers or (except for tgr0b and tgr0d of channel 0) as input capture registers. the channel 0 tgrc and tgrd registers can be used as buffer registers. ? can select six counter input clock sources for all channels ? all channels can be set for the following operating modes: ? compare match waveform output: 0 output/1 output/toggle output selectable. ? input capture function: selectable rising edge, falling edge, or both rising and falling edge detection. ? counter clearing function: counters can be cleared by a compare-match or input capture. ? synchronizing mode: two or more timer counters (tcnt) can be written to simultaneously. two or more timer counters can be simultaneously cleared by a compare- match or input capture. counter synchronization functions enable synchronized register input/output. ? pwm mode: pwm output can be provided with any duty cycle. when combined with the counter synchronizing function, enables up to four-phase* pwm output. note: * when channels 0 to 2 are set to pwm mode 1 ? channel 0 can be set for buffer operation ? input capture register double buffer configuration possible ? output compare register automatic re-write possible ? cascade connection operation ? can be operated as a 32-bit counter by using the channel 2 input clock for channel 1 overflow/underflow ? high speed access via internal 16-bit bus ? eleven interrupt sources ? channel 0 has two dual-function compare-match/input capture interrupts, two compare- match interrupts, and one overflow interrupt, which can be requested independently. 90 ? channels 1 and 2 have two compare-match/input capture interrupts, one overflow interrupt, and one underflow interrupt which can be requested independently. ? a/d converter conversion start trigger can be generated ? channel 0 to 2 compare-match/input capture signals can be used as a/d converter conversion start triggers. 91 table 8.1 summarizes the mtu functions. table 8.1 mtu functions item channel 0 channel 1 channel 2 counter clocks internal: f/ 1, f /4, f /16, f /64, f /256, f /1024 six to each channel general registers tgr0a tgr0b tgr1a tgr1b tgr2a tgr2b general registers/buffer registers tgr0c tgr0d no no input/output pins tioc0a tioc0c tioc1a tioc2a counter clear function tgr compare-match or input capture tgr compare-match or input capture tgr compare-match or input capture compare 0 yes yes yes match 1 yes yes yes output toggle yes yes yes input capture function yes yes yes synchronization yes yes yes buffer operation yes no no pwm mode 1 yes yes yes pwm mode 2 yes yes yes a/d conversion start trigger tgr0a compare match or input capture tgr1a compare match or input capture tgr2a compare match or input capture interrupt sources compare match/input capture 0a compare match/input capture 1a compare match/input capture 2a compare match 0b compare match/input capture 1b compare match/input capture 2b compare match/input capture 0c overflow overflow compare match 0d overflow 92 8.1.2 block diagram figure 8.1 is the block diagram of the mtu. [clock input] internal clock: f /1 f /4 f /16 f /64 f /256 f /1024 [interrupt request signal] channel 0: tgi0a tgi0b tgi0c tgi0d tci0v channel 1: tgi1a tgi1b tci1v channel 2: tgi2a tgi2b tci2v [i/o pins] channel 0: tioc0a tioc0c channel 1: tioc1a tioc1b channel 2: tioc2a tioc2b internal data bus a/d conversion start request signal bus i/f shared tsyr tstr control logic module data bus channel 0? control logic tcnt tgra tgrb tgrc tgrd tcnt tgra tgrb tcnt tgra tgrb channel 2 channel 1 channel 0 tcr tiorh tier tmdr tiorl tsr tcr tior tier tmdr tsr tcr tior tier tmdr tsr figure 8.1 mtu block diagram 93 8.1.3 pin configuration table 8.2 summarizes the mtu pins. table 8.2 pin configuration channel name pin name i/o function 0 input capture/output compare-match 0a tioc0a i/o tgr0a input capture input/output compare output/pwm output pin input capture/output compare-match 0c tioc0c i/o tgr0c input capture input/output compare output/pwm output pin 1 input capture/output compare-match 1a tioc1a i/o tgr1a input capture input/output compare output/pwm output pin input capture/output compare-match 1b tioc1b i/o tgr1b input capture input/output compare output/pwm output pin 2 input capture/output compare-match 2a tioc2a i/o tgr2a input capture input/output compare output/pwm output pin input capture/output compare-match 2b tioc2b i/o tgr2b input capture input/output compare output/pwm output pin note: the tioc pins output undefined values when they are set to input capture and timer output by the pin function controller (pfc). 94 8.1.4 register configuration table 8.3 summarizes the mtu register configuration. table 8.3 register configuration chan- nel name abbrevi- ation r/w initial value address access size (bits) * 1 shared timer start register tstr r/w h'00 h'ffff8240 8, 16 timer synchro register tsyr r/w h'00 h'ffff8241 0 timer control register 0 tcr0 r/w h'00 h'ffff8260 8, 16, 32 timer mode register 0 tmdr0 r/w h'c0 h'ffff8261 timer i/o control register 0h tior0h r/w h'00 h'ffff8262 timer i/o control register 0l tior0l r/w h'00 h'ffff8263 timer interrupt enable register 0 tier0 r/w h'40 h'ffff8264 timer status register 0 tsr0 r/(w)* 2 h'c0 h'ffff8265 timer counter 0 tcnt0 r/w h'0000 h'ffff8266 16, 32 general register 0a tgr0a r/w h'ffff h'ffff8268 general register 0b tgr0b r/w h'ffff h'ffff826a general register 0c tgr0c r/w h'ffff h'ffff826c general register 0d tgr0d r/w h'ffff h'ffff826e 1 timer control register 1 tcr1 r/w h'00 h'ffff8280 8, 16 timer mode register 1 tmdr1 r/w h'c0 h'ffff8281 timer i/o control register 1 tior1 r/w h'00 h'ffff8282 8 timer interrupt enable register 1 tier1 r/w h'40 h'ffff8284 8, 16, 32 timer status register 1 tsr1 r/(w)* 2 h'c0 h'ffff8285 timer counter 1 tcnt1 r/w h'0000 h'ffff8286 16, 32 general register 1a tgr1a r/w h'ffff h'ffff8288 general register 1b tgr1b r/w h'ffff h'ffff828a 95 table 8.3 register configuration (cont) chan- nel name abbrevi- ation r/w initial value address access size (bits) * 1 2 timer control register 2 tcr2 r/w h'00 h'ffff82a0 8, 16 timer mode register 2 tmdr2 r/w h'c0 h'ffff82a1 timer i/o control register 2 tior2 r/w h'00 h'ffff82a2 8 timer interrupt enable register 2 tier2 r/w h'40 h'ffff82a4 8, 16, 32 timer status register 2 tsr2 r/(w)* 2 h'c0 h'ffff82a5 timer counter 2 tcnt2 r/w h'0000 h'ffff82a6 16, 32 general register 2a tgr2a r/w h'ffff h'ffff82a8 general register 2b tgr2b r/w h'ffff h'ffff82aa notes: do not access empty addresses. 1. 16-bit registers (tcnt, tgr) cannot be read or written in 8-bit units. 2. write 0 to clear flags. 8.2 mtu register descriptions 8.2.1 timer control register (tcr) the tcr is an 8-bit read/write register for controlling the tcnt counter for each channel. the mtu has three tcr registers, one for each of the channels 0 to 2. tcr is initialized to h'00 by a power-on reset or the standby mode. channel 0: tcr0 bit: 7 6 5 4 3 2 1 0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w channels 1, 2: tcr1, tcr2 bit: 7 6 5 4 3 2 1 0 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w 96 ? bits 7??ounter clear 2, 1, 0 (cclr2, cclr1, cclr0): select the counter clear source for the tcnt counter. channels 0: bit 7: cclr2 bit 6: cclr1 bit 5: cclr0 description 0 0 0 tcnt clear disabled (initial value) 1 tcnt is cleared by tgra compare-match or input capture 1 0 tcnt is cleared by tgrb compare-match 1 synchronizing clear: tcnt is cleared in synchronization with clear of other channel counters operating in sync.* 1 1 0 0 tcnt clear disabled 1 tcnt is cleared by tgrc compare-match or input capture* 2 1 0 tcnt is cleared by tgrd compare-match* 2 1 synchronizing clear: tcnt is cleared in synchronization with clear of other channel counters operating in sync* 1 notes: 1. setting the sync bit of the tsyr to 1 sets the synchronization. 2. when tgrc or tgrd are functioning as buffer registers, tcnt is not cleared because the buffer registers have priority and compare-match/input captures do not occur. channels 1, 2: bit 7: reserved* 1 bit 6: cclr1 bit 5: cclr0 description 0 0 0 tcnt clear disabled (initial value) 1 tcnt is cleared by tgra compare-match or input capture 1 0 tcnt is cleared by tgrb compare-match or input capture 1 synchronizing clear: tcnt is cleared in synchronization with clear of other channel counters operating in sync* 2 notes: 1. the bit 7 of channels 1 and 2 is reserved. it always reads 0, and cannot be modified. 2. setting the sync bit of the tsyr to 1 sets the synchronization. ? bits 4??lock edge 1, 0 (ckeg1 and ckeg0): ckeg1 and ckeg0 select the input clock edges. when counting is done on both edges of the internal clock the input clock frequency becomes 1/2 (example: both edges of f/4 = rising edge of f/2 ). 97 bit 4: ckeg1 bit 3: ckeg0 description 0 0 count on rising edges (initial value) 1 count on falling edges 1 x count on both rising and falling edges notes: 1. x: 0 or 1, don? care. 2. internal clock edge selection is effective when the input clock is f /4 or slower. these settings are ignored when f /1, or the overflow of another channel is selected for the input clock. ? bits 2??imer prescaler 2? (tpsc2?psc0): tpsc2?psc0 select the counter clock source for the tcnt. an independent clock source can be selected for each channel. table 8.4 shows the possible settings for each channel. table 8.4 mtu clock sources internal clock other channel channel f /1 f /4 f /16 f /64 f /256 f /1024 overflow 0 oooox x x 1 ooooox o 2 oooox ox note: symbols: o: setting possible x: setting not possible channel 0: bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 0 0 0 internal clock: count with f /1 (initial value) 1 internal clock: count with f /4 1 0 internal clock: count with f /16 1 internal clock: count with f /64 1 0 0 reserved (do not set) 1 reserved (do not set) 1 0 reserved (do not set) 1 reserved (do not set) 98 channel 1: bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 0 0 0 internal clock: count with f /1 (initial value) 1 internal clock: count with f /4 1 0 internal clock: count with f /16 1 internal clock: count with f /64 1 0 0 reserved (do not set) 1 reserved (do not set) 1 0 internal clock: count with f /256 1 count with the tcnt2 overflow channel 2: bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 0 0 0 internal clock: count with f /1 (initial value) 1 internal clock: count with f /4 1 0 internal clock: count with f /16 1 internal clock: count with f /64 1 0 0 reserved (do not set) 1 reserved (do not set) 1 0 reserved (do not set) 1 internal clock: count with f /1024 99 8.2.2 timer mode register (tmdr) the tmdr is an 8-bit read/write register that sets the operating mode for each channel. the mtu has three tmdr registers, one for each channel. tmdr is initialized to h'c0 by a power-on reset. channel 0: tmdr0 bit: 7 6 5 4 3 2 1 0 bfb bfa md3 md2 md1 md0 initial value: 1 1 0 0 0 0 0 0 r/w: r r r/w r/w r/w r/w r/w r/w channels 1, 2: tmdr1, tmdr2 bit: 7 6 5 4 3 2 1 0 md3 md2 md1 md0 initial value: 1 1 0 0 0 0 0 0 r/w: r r r r r/w r/w r/w r/w ? bits 7, 6?eserved: these bits are reserved. they always read as 1, and cannot be modified. ? bit 5?uffer operation b (bfb): designates whether to use the tgrb register for normal operation, or buffer operation in combination with the tgrd register. when using tgrd as a buffer register, no tgrd register input capture/output compares are generated. this bit is reserved in channels 1 and 2, which have no tgrd registers. it is always read as 0, and cannot be modified. bit 5: bfb description 0 tgrb operates normally (initial value) 1 tgrb and tgrd buffer operation ? bit 4?uffer operation a (bfa): designates whether to use the tgra register for normal operation, or buffer operation in combination with the tgrc register. when using tgrc as a buffer register, no tgrc register input capture/output compares are generated. this bit is reserved in channels 1 and 2, which have no tgrc registers. it is always read as 0, and cannot be modified. bit 4: bfa description 0 tgra operates normally (initial value) 1 tgra and tgrc buffer operation 100 ? bits 3??odes 3? (md3?d0): these bits set the timer operation mode. bit 3: md3 bit 2: md2 bit 1: md1 bit 0: md0 description 0000 normal operation (initial value) 1 reserved (do not set) 1 0 pwm mode 1 1 pwm mode 2 0 1 * * reserved (do not set) 1 * * * reserved (do not set) *: don? care 8.2.3 timer i/o control register (tior) the tior is a register that controls the tgr. the mtu has four tior registers, two for channels 0, and one each for channels 1 and 2. tior is initialized to h'00 by a power-on reset. channel 0: tior0h bit: 7 6 5 4 3 2 1 0 ioa3 ioa2 ioa1 ioa0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r/w r/w r/w r/w channels 1, 2: tior1, tior2 bit: 7 6 5 4 3 2 1 0 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 7??/o control b3?0 (iob3?ob0): these bits set the tgrb register function. (tior1 and tior2 only. tior0h is a reserved bit: it always reads 0 and its write value should always be 0.) bits 3??/o control a3?0 (ioa3?oa0): these bits set the tgra register function. 101 channel 0: tior0l bit: 7 6 5 4 3 2 1 0 ioc3 ioc2 ioc1 ioc0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r/w r/w r/w r/w note: when the tgrc or tgrd registers are set for buffer operation, these settings become ineffective and the operation is as a buffer register. ? bits 7??eserved. these bits always read 0. the write value should always be 0. ? bits 3??/o control c3?0 (ioc3?oc0): these bits set the tgrc register function. channel 0 (tior0h register): ? bits 7??eserved. these bits always read 0. the write value should always be 0. ? bits 3??/o control a3?0 (ioa3?oa0): these bits set the tgr0a register function. bit 3: ioa3 bit 2: ioa2 bit 1: ioa1 bit 0: ioa0 description 0 0 0 0 tgr0a output disabled (initial value) 1 is an initial output 0 on compare-match 10 output output output 1 on compare-match 1 compare is 0 toggle output on compare-match 10 0 register output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match 1 0 0 0 tgr0a capture input capture on rising edge 1 is an input source input capture on falling edge 10 input is the input capture on both edges 1 capture tioc0a pin 10 0 register capture input capture 1 input source on tcnt1 10 is channel 1/ count up/count down 1 count clock 102 channel 0 (tior0l register): ? bits 7??eserved. these bits always read 0. the write value should always be 0. ? bits 3??/o control c3?0 (ioc3?oc0): these bits set the tgr0c register function. bit 3: ioc3 bit 2: ioc2 bit 1: ioc1 bit 0: ioc0 description 0 0 0 0 tgr0c output disabled (initial value) 1 is an initial output 0 on compare-match 10 output output output 1 on compare-match 1 compare is 0 toggle output on compare-match 10 0 register output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match 1 0 0 0 tgr0c capture input capture on rising edge 1 is an input source input capture on falling edge 10 input is the input capture on both edges 1 capture tioc0c pin 10 0 register capture input capture 1 input source on tcnt1 10 is channel 1/ count up/count down 1 count clock note: when the bfa bit of tmdr0 is set to 1 and tgr0c is being used as a buffer register, these settings become ineffective and input capture/output compares do not occur. 103 channel 1 (tior1 register): ? bits 7??/o control b3?0 (iob3?ob0): these bits set the tgr1b register function. bit 7: iob3 bit 6: iob2 bit 5: iob1 bit 4: iob0 description 0 0 0 0 tgr1b output disabled (initial value) 1 is an initial output 0 on compare-match 10 output output output 1 on compare-match 1 compare is 0 toggle output on compare-match 10 0 register output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match 1 0 0 0 tgr1b capture input capture on rising edge 1 is an input source input capture on falling edge 10 input is the input capture on both edges 1 capture tioc1b pin 10 0 register capture input input capture 1 source tgr0c on channel tgr0c 10 compare/match compare-match/input 1 input capture capture generation 104 ? bits 3??/o control a3?0 (ioa3?oa0): these bits set the tgr1a register function. bit 3: ioa3 bit 2: ioa2 bit 1: ioa1 bit 0: ioa0 description 0 0 0 0 tgr1a output disabled (initial value) 1 is an initial output 0 on compare-match 10 output output output 1 on compare-match 1 compare is 0 toggle output on compare-match 10 0 register output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match 1 0 0 0 tgr1a capture input capture on rising edge 1 is an input source input capture on falling edge 10 input is the input capture on both edges 1 capture tioc1a pin 10 0 register capture input input capture 1 source is tgr0a on channel 0/tgr0a 10 compare- match/input compare-match/input capture generation 1 capture 105 channel 2 (tior2 register): ? bits 7??/o control b3?0 (iob3?ob0): these bits set the tgr2b register function. bit 7: iob3 bit 6: iob2 bit 5: iob1 bit 4: iob0 description 0 0 0 0 tgr2b output disabled (initial value) 1 is an initial output 0 on compare-match 10 output output output 1 on compare-match 1 compare is 0 toggle output on compare-match 10 0 register output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match 1 0 0 0 tgr2b capture input capture on rising edge 1 is an input source input capture on falling edge 10 input is the input capture on both edges 1 capture tioc2b pin 10 0 register input capture on rising edge 1 input capture on falling edge 1 0 input capture on both edges 1 106 ? bits 3??/o control a3?0 (ioa3?oa0): these bits set the tgr2a register function. bit 3: ioa3 bit 2: ioa2 bit 1: ioa1 bit 0: ioa0 description 0 0 0 0 tgr2a output disabled (initial value) 1 is an initial output 0 on compare-match 10 output output output 1 on compare-match 1 compare is 0 toggle output on compare-match 10 0 register output disabled 1 initial output 0 on compare-match 10 output output 1 on compare-match 1 is 1 toggle output on compare-match 1 0 0 0 tgr2a capture input capture on rising edge 1 is an input source input capture on falling edge 10 input is the input capture on both edges 1 capture tioc2a pin 10 0 register input capture on rising edge 1 input capture on falling edge 1 0 input capture on both edges 1 107 8.2.4 timer interrupt enable register (tier) the tier is an 8-bit register that controls the enable/disable of interrupt requests for each channel. the mtu has three tier registers, one each for channel. tier is initialized to h'40 by a power- on reset. channel 0: tier0 bit: 7 6 5 4 3 2 1 0 ttge tciev tgied tgiec tgieb tgiea initial value: 0 1 0 0 0 0 0 0 r/w: r/w r r r/w r/w r/w r/w r/w channels 1, 2: tier1, tier2 bit: 7 6 5 4 3 2 1 0 ttge tciev tgieb tgiea initial value: 0 1 0 0 0 0 0 0 r/w: r/w r r r/w r r r/w r/w ? bit 7?/d conversion start request enable (ttge): enables or disables generation of an a/d conversion start request by a tgra register input capture/compare-match. bit 7: ttge description 0 disable a/d conversion start requests generation (initial value) 1 enable a/d conversion start request generation ? bit 6?eserved: this bit is reserved. it always reads as 1, and cannot be modified. ? bit 5?eserved. this bit always reads 0. the write value should always be 0. ? bit 4?verflow interrupt enable (tciev): enables or disables interrupt requests when the overflow flag tcfv of the timer status register (tsr) is set to 1. bit 4: tciev description 0 disable tcfv interrupt requests (tciv) (initial value) 1 enable tcfv interrupt requests (tciv) 108 ? bit 3?gr interrupt enable d (tgied): enables or disables interrupt tgfd requests when the tgfd bit of the channel 0 of the tsr register is set to 0. this bit is reserved for channels 1 and 2. it always reads as 0. the write value should always be 0. bit 3: tgied description 0 disable interrupt requests (tgid) due to the tgfd bit (initial value) 1 enable interrupt requests (tgid) due to the tgfd bit ? bit 2?gr interrupt enable c (tgiec): enables or disables tgfc interrupt requests when the tgfc bit of the channel 0 of the tsr register is set to 1. this bit is reserved for channels 1 and 2. it always reads as 0. the write value should always be 0. bit 2: tgiec description 0 disable interrupt requests (tgic) due to the tgfc bit (initial value) 1 enable interrupt requests (tgic) due to the tgfc bit ? bit 1?gr interrupt enable b (tgieb): enables or disables tgfb interrupt requests when the tgfb bit of the tsr register is set to 1. bit 1: tgieb description 0 disable interrupt requests (tgib) due to the tgfb bit (initial value) 1 enable interrupt requests (tgib) due to the tgfb bit ? bit 0?gr interrupt enable a (tgiea): enables or disables tgfa interrupt requests when the tgfa bit of the tsr register is set to 1. bit 0: tgiea description 0 disable interrupt requests (tgia) due to the tgfa bit (initial value) 1 enable interrupt requests (tgia) due to the tgfa bit 109 8.2.5 timer status register (tsr) the timer status register (tsr) is an 8-bit register that indicates the status of each channel. the mtu has three tsr registers, one each for channel. tsr is initialized to h'c0 by a power-on reset. channel 0: tsr0 bit: 7 6 5 4 3 2 1 0 tcfv tgfd tgfc tgfb tgfa initial value: 1 1 0 0 0 0 0 0 r/w: r r r r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* note: only 0 writes to clear the flags are possible. channels 1, 2: tsr1, tsr2 bit: 7 6 5 4 3 2 1 0 tcfv tgfb tgfa initial value: 1 1 0 0 0 0 0 0 r/w: r r r r/(w)* r r r/(w)* r/(w)* note: only 0 writes to clear the flags are possible. ? bits 7 and 6?eserved. these bits always read 1. the write value should always be 1. ? bit 5?eserved. this bit always reads 0. the write value should always be 0. ? bit 4?verflow flag (tcfv): this status flag indicates the occurrence of a tcnt counter overflow. bit 4: tcfv description 0 clear condition: with tcfv =1, a 0 write to tcfv after reading it (initial value) 1 set condition: when the tcnt value overflows (h'ffff h'0000) 110 ? bit 3?utput compare flag d (tgfd): this status flag indicates the occurrence of a channel 0 tgrd register compare-match. this bit is reserved in channels 1 and 2: it always reads 0 and the write value should always be 0. bit 3: tgfd description 0 clear condition: with tgfd = 1, a 0 write to tgfd following a read (initial value) 1 set condition: when tcnt = tgrd while tgrd is functioning as an output compare register ? bit 2?nput capture/output compare flag c (tgfc): this status flag indicates the occurrence of a channel 0 tgrc register input capture or compare-match. this bit is reserved for channels 1 and 2. it always reads as 0. the write value should always be 0. bit 2: tgfc description 0 clear condition: with tgfc = 1, a 0 write to tgfc following a read (initial value) 1 set conditions: ? when tgrc is functioning as an output compare register (tcnt = tgrc) ? when tgrc is functioning as input capture (the tcnt value is sent to tgrc by the input capture signal) ? bit 1?utput compare flag b (tgfb): this status flag indicates the occurrence of a tgrb register compare-match. bit 1: tgfb description 0 clear condition: with tgfb = 1, a 0 write to tgfb following a read (initial value) 1 set conditions: when tgrb is functioning as an output compare register (tcnt = tgrb) 111 ? bit 0?nput capture/output compare flag a (tgfa): this status flag indicates the occurrence of a tgra register input capture or compare-match. bit 0: tgfa description 0 clear condition: with tgfa = 1, a 0 write to tgfa following a read (initial value) 1 set conditions: ? when tgra is functioning as an output compare register (tcnt = tgra) ? when tgra is functioning as input capture (the tcnt value is sent to tgra by the input capture signal) 8.2.6 timer counters (tcnt) the timer counters (tcnt) are 16-bit counters, with one for each channel, for a total of three. the tcnt are initialized to h'0000 by a power-on reset. accessing the tcnt counters in 8-bit units is prohibited. always access in 16-bit units. channel 0: tcnt0 channel 1: tcnt1 channel 2: tcnt2 bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 112 8.2.7 timer general register (tgr) each timer general register (tgr) is a 16-bit register that can function as either an output compare register or an input capture register. there are a total of eight tgr, four each for channels 0 and two each for channels 1 and 2. the tgrc and tgrd of channels 0 can be set to operate as buffer registers. the tgr register and buffer register combinations are tgra with tgrc, and tgrb with tgrd. the tgrs are initialized to h'ffff by a power-on reset. accessing of the tgrs in 8-bit units is disabled; they may only be accessed in 16-bit units. bit: 15 14 13 12 11 10 9 8 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 8.2.8 timer start register (tstr) the timer start register (tstr) is an 8-bit read/write register that starts and stops the timer counters (tcnt) of channels 0?. tstr is initialized to h'00 upon power-on reset. bit: 7 6 5 4 3 2 1 0 cst2 cst1 cst0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w ? bits 7??eserved. these bits always read 0. the write value should always be 0. ? bits 2??ounter start 2-0 (cst2-cst0): select starting and stopping of the timer counters (tcnt). the corresponding between bits and channels is as follows: cst2: channel 2 (tcnt2) cst1: channel 1 (tcnt1) cst0: channel 0 (tcnt0) 113 bit n: cstn description 0 tcntn count is halted (initial value) 1 tcntn counts note: n = 2 to 0. if 0 is written to a cst bit during operation with the tioc pin in the output state, the counter stops, but the tioc pin output compare output level is maintained. if a write is performed on the tior register while a cst bit is 0, the pin output level is updated to the set initial output value. 8.2.9 timer synchro register (tsyr) the timer synchro register (tsyr) is an 8-bit read/write register that selects independent or synchronous tcnt counter operation for channels 0?. channels for which 1 is set in the corresponding bit will be synchronized. tsyr is initialized to h'00 upon power-on reset. bit: 7 6 5 4 3 2 1 0 sync2 sync1 sync0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w ? bits 7??eserved. these bits always read 0. the write value should always be 0. ? bits 2??imer synchronization 2? (sync2?ync0): selects operation independent of, or synchronized to, other channels. synchronous operation allows synchronous clears due to multiple tcnt synchronous presets and other channel counter clears. a minimum of two channels must have sync bits set to 1 for synchronous operation. for synchronization clearing, it is necessary to set the tcnt counter clear sources (the cclr2?clr0 bits of the tcr register), in addition to the sync bit. the counter start to channel and bit-to-channel correspondence are indicated in the tables below. sync2: channel 2 (tcnt2) sync1: channel 1 (tcnt1) sync0: channel 0 (tcnt0) 114 bit n: syncn description 0 timer counter (tcntn) independent operation (initial value) (tcntn preset/clear unrelated to other channels) 1 timer counter synchronous operation* 1 tcntn synchronous preset/ synchronous clear* 2 possible note: 1. minimum of two channel sync bits must be set to 1 for synchronous operation. 2. tcnt counter clear sources (cclr2?clr0 bits of the tcr register) must be set in addition to the sync bit in order to have clear synchronization. n = 2 to 0. 8.3 bus master interface 8.3.1 16-bit registers the timer counters (tcnt) and general registers (tgr) are 16-bit registers. a 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit read/write is not possible. always access in 16-bit units. figure 8.3 shows an example of 16-bit register access operation. tcnth bus interface upper 8 bits lower 8 bits bus master internal data bus module data bus tcntl figure 8.2 16-bit register access operation (bus master tcnt (16 bit)) 8.3.2 8-bit registers all registers other than the tcnt and general registers (tgr) are 8-bit registers. these are connected to the cpu by a 16-bit data bus, so 16-bit read/writes and as 8-bit read/writes are both possible (figures 8.3, 8.4, 8.5). 115 tcr bus interface upper 8 bits lower 8 bits bus master internal data bus module data bus figure 8.3 8-bit register access operation (bus master tcr (upper 8 bits)) tmdr bus interface upper 8 bits lower 8 bits bus master internal data bus module data bus figure 8.4 8-bit register access operation (bus master tmdr (lower 8 bits)) tcr tmdr bus interface upper 8 bits lower 8 bits bus master internal data bus module data bus figure 8.5 8-bit register access operation (bus master tcr, tmdr (16 bit)) 116 8.4 operation 8.4.1 overview the operation modes are described below. ordinary operation: each channel has a timer counter (tcnt) and general register (tgr). the tcnt is an upcounter and can also operate as a free-running counter, periodic counter or external event counter. general registers (tgr) can be used as output compare registers or input capture registers. synchronized operation: the tcnt of a channel set for synchronized operation does a synchronized preset. when any tcnt of a channel operating in the synchronized mode is rewritten, the tcnts of other channels are simultaneously rewritten as well. the timer synchronization bits of the tsyr registers of multiple channels set for synchronous operation can be set to clear the tcnts simultaneously. buffer operation: when tgr is an output compare register, the buffer register value of the corresponding channel is transferred to the tgr when a compare-match occurs. when tgr is an input capture register, the tcnt counter value is transferred to the tgr when an input capture occur simultaneously the value previously stored in the tgr is transferred to the buffer register. cascade connection operation : the channel 1 and channel 2 counters (tcnt1 and tcnt2) can be connected together to operate as a 32-bit counter. pwm mode: in pwm mode, a pwm waveform is output. the output level can be set by the tior register. each tgr can be set for pwm waveform output with a duty cycle between 0% and 100%. 8.4.2 basic functions always select mtu external pin set function using the pin function controller (pfc). counter operation: when a start bit (cst0?st2) in the timer start register (tstr) is set to 1, the corresponding timer counter (tcnt) starts counting. there are two counting modes: a free- running mode and a periodic mode. to select the counting operation (figure 8.6): 1. set bits tpsc2?psc0 in the tcr to select the counter clock. at the same time, set bits ckeg1 and ckeg0 in the tcr to select the desired edge of the input clock. 2. to operate as a periodic counter, set the cclr2?clr0 bits in the tcr to select tgr as a clearing source for the tcnt. 117 3. set the tgr selected in step 2 as an output compare register using the timer i/o control register (tior). 4. write the desired cycle value in the tgr selected in step 2. 5. set the cst bit in the tstr to 1 to start counting. counting mode selection select counter clock periodic counter select counter clear source select output compare register set period start counting start counting free-running counter periodic counter free-running counter (5) (5) (4) (3) (2) (1) figure 8.6 procedure for selecting the counting operation free-running counter operation example: a reset of the mtu timer counters (tcnt) leaves them all in the free-running mode. when a bit in the tstr is set to 1, the corresponding timer counter operates as a free-running counter and begins to increment. when the count overflows from h'ffff?'0000, the tcfv bit in the timer status register (tsr) is set to 1. if the tciev bit in the timer? corresponding timer interrupt enable register (tier) is set to 1, the mtu will make an interrupt request to the interrupt controller. after the tcnt overflows, counting continues from h'0000. figure 8.7 shows an example of free-running counter operation. 118 cst bit tcnt value time h'ffff h'0000 tcfv figure 8.7 free-running counter operation periodic counter operation example: periodic counter operation is obtained for a given channel? tcnt by selecting compare-match as a tcnt clear source. set the tgr register for period setting to output compare register and select counter clear upon compare-match using the cclr2?clr0 bits of the timer control register (tcr). after these settings, the tcnt begins incrementing as a periodic counter when the corresponding bit of tstr is set to 1. when the count matches the tgr register value, the tgf bit in the tsr is set to 1 and the counter is cleared to h'0000. if the tgie bit of the corresponding tier is set to 1 at this point, the mtu will make an interrupt request to the interrupt controller. after the compare-match, tcnt continues counting from h'0000. figure 8.8 shows an example of periodic counting. cst bit tcnt value time counter cleared by tgr compare match tgr h'0000 tgf flag cleared by software activation figure 8.8 periodic counter operation 119 compare-match waveform output function: the mtu can output 0 level, 1 level, or toggle output from the corresponding output pins upon compare-matches. procedure for selecting the compare-match waveform output operation (figure 8.9): 1. set the tior to select 0 output or 1 output for the initial value, and 0 output, 1 output, or toggle output for compare-match output. the tioc pin will output the set initial value until the first compare-match occurs. 2. set a value in the tgr to select the compare-match timing. 3. set the cst bit in the tstr to 1 to start counting. output selection select waveform output mode select output timing start counting (1) (2) (3) figure 8.9 procedure for selecting compare match waveform output operation waveform output operation (0 output/1 output): figure 8.10 shows 0 output/1 output. in the example, tcnt is a free-running counter, 1 is output upon compare-match a and 0 is output upon compare-match b. when the pin level matches the set level, the pin level does not change. 120 h'ffff h'0000 tioca tcnt value time tgra tgrb tiocb does not change does not change 1 output does not change does not change 0 output figure 8.10 example of 0 output/1 output waveform output operation (toggle output): figure 8.11 shows the toggle output. in the example, the tcnt operates as a periodic counter cleared by compare-match b, with toggle output at both compare-match a and compare-match b. h'ffff h'0000 tioca tcnt value counter cleared by tgrb compare match time tgrb tgra tiocb toggle output toggle output figure 8.11 example of toggle output input capture function: in the input capture mode, the tcnt value is transferred into the tgr register when the input edge is detected at the input capture/output compare pin (tioc). detection can take place on the rising edge, falling edge, or both edges. channels 0 and 1 can use other channel counter input clocks or compare-match signals as input capture sources. 121 the procedure for selecting the input capture operation (figure 8.12) is: 1. set the tior to select the input capture function of the tgr, then select the input capture source, and rising edge, falling edge, or both edges as the input edge. 2. set the cst bit in the tstr to 1 to start the tcnt counting. input selection select input-capture input start counting input capture operation (1) (2) figure 8.12 procedure for selecting input capture operation input capture operation: figure 8.13 shows input capture. the falling edge of tiocb and both edges of tioca are selected as input capture input edges. in the example, tcnt is set to clear at the input capture of the tgrb register. counter cleared by tiocb input (falling edge) tcnt value h'0180 h'0160 h'0005 h'0010 h'0000 tiocb tioca tgra tgrb h'0005 h'0160 h'0010 h'0180 time figure 8.13 input capture operation 122 8.4.3 synchronous operation there are two kinds of synchronous operation, synchronized preset and synchronized clear. the synchronized preset operation allows multiple timer counters (tcnt) to be rewritten simultaneously, while the synchronized clear operation allows multiple tcnt counters to be cleared simultaneously using timer control register (tcr) settings. the synchronizing mode can increase the number of tgr registers for a single time base. all five channels can be set for synchronous operation. procedure for selecting the synchronizing mode (figure 8.14): 1. set 1 in the sync bit of the timer synchro register (tsyr) to use the corresponding channel in the synchronizing mode. 2. when a value is written in the tcnt in any of the synchronized channels, the same value is simultaneously written in the tcnt in the other channels. 3. set the counter to clear with output compare/input capture using bits cclr2?clr0 in the tcr. 4. set the counter clear source to synchronized clear using the cclr2?clr0 bits of the tcr. 5. set the cst bits for the corresponding channels in the tstr to 1 to start counting in the tcnt. select counter clear source channel that generated clear source? no yes select synchronizing mode set synchronizing mode synchronized preset set tcnt start counting set counter synchronous clear start counting counter clear synchronized clear synchronized preset synchronized clear (1) (2) (3) (5) (4) (5) figure 8.14 procedure for selecting synchronizing operation 123 synchronized operation: figure 8.15 shows an example of synchronized operation. channels 0, 1, and 2 are set to synchronized operation and pwm mode 1. channel 0 is set for a counter clear upon compare-match with tgr0b. channels 1 and 2 are set for synchronous counter clears by synchronous presets and tgr0b register compare-matches. accordingly, a three-phase pwm waveform with the data set in the tgr0b register as its pwm period is output from the tioc0a, tioc1a, and tioc2a pins. see section 8.4.6, pwm mode, for details on the pwm mode. tcnt0?cnt2 values time tioc0a synchronized clear on tgr0b compare match tgr0b tgr1b tgr0a tgr2b tgr1a tgr2a h'0000 tioc1a tioc2a figure 8.15 synchronized operation example 124 8.4.4 buffer operation buffer operation is a function of channel 0. tgrc and tgrd can be used as buffer registers. table 8.5 shows the register combinations for buffer operation. table 8.5 register combinations channel general register buffer register 0 tgr0a tgr0c tgr0b tgr0d the buffer operation differs, depending on whether the tgr has been set as an input capture register or an output compare register. when tgr is an output compare register: when a compare-match occurs, the corresponding channel buffer register value is transferred to the general register. figure 8.16 shows an example. compare match signal buffer register tcnt comparator general register figure 8.16 compare match buffer operation when tgr is an input capture register: when an input capture occurs, the timer counter (tcnt) value is transferred to the general register (tgr), and the value that had been held up to that time in the tgr is transferred to the buffer register (figure 8.17). input capture signal tcnt buffer register general register figure 8.17 input capture buffer operation 125 procedure for setting buffer mode (figure 8.18): 1. use the timer i/o control register (tior) to set the tgr as either an input capture or output compare register. 2. use the timer mode register (tmdr) bfa, and bfb bits to set the tgr for buffer mode. 3. set the cst bit in the tstr to 1 to start the count operation. (1) (2) (3) select tgr function buffer mode select buffer mode start counting buffer mode figure 8.18 buffer operation setting procedure buffer operation examples?hen tgr is an output compare register: figure 8.19 shows an example of channel 0 set to pwm mode 1, and the tgra and tgrc registers set for buffer operation. the tcnt counter is cleared by a compare-match b, and the output is a 1 upon compare-match a and 0 output upon compare-match b. because buffer mode is selected, a compare-match a changes the output, and the buffer register tgrc value is simultaneously transferred to the general register tgra. this operation is repeated with each occurrence of a compare-match a. see section 8.4.6, pwm mode, for details on the pwm mode. 126 tgr0b tgr0a h'0000 tgr0c tgr0a tioc0a h'0450 h'0520 h'0200 h'0450 h'0520 h'0200 tcnt value time transfer h'0450 h'0200 figure 8.19 buffer operation example (output compare register) buffer operation examples?hen tgr is an input capture register: figure 8.20 shows an example of tgra set as an input capture register with the tgra and tgrb registers set for buffer operation. the tcnt counter is cleared by a tgra register input capture, and the tioca pin input capture input edge is selected as both rising and falling edge. because buffer mode is selected, an input capture a causes the tcnt counter value to be stored in the tgra register, and the value that was stored in the tgra up until that time is simultaneously transferred to the tgrc register. h'0f07 h'09fb h'0532 h'0000 tgra tgrc tioc0a h'0532 h'09fb h'0f07 tcnt value time h'0f07 h'0532 figure 8.20 buffer operation example (input capture register) 127 8.4.5 cascade connection mode cascade connection mode is a function that connects the 16-bit counters of two channels together to act as a 32-bit counter. this function operates by using the tpsc2?psc0 bits of the tcr register to set the channel 1 counter clock to count by tcnt2 counter overflow. table 8.6 shows the cascade connection combinations. table 8.6 cascade connection combinations combination upper 16 bits lower 16 bits channel 1, channel 2 tcnt1 tcnt2 procedure for setting cascade connection mode (figure 8.21): 1. set the tpsc2?psc 0 bits of the channel 1 timer control register (tcr) to b'111 to select ?ount by tcnt2 overflow. 2. set the cst bits corresponding to the upper and lower 16 bits in the tstr to 1 to start the count operation. cascade connection operation select cascade connection start counting cascade connection operation (1) (2) figure 8.21 procedure for selecting cascade connection mode cascade connection mode examples?nput capture: figure 8.22 shows an example of operation when the tcnt1 counter is set to count on tcnt2 overflow, the tgr1a and tgr2a registers are set as input capture registers, and the tioc pin rising edge is selected. through simultaneous input of the rising edge to the tioc1a and tioc2a pins, 32-bit data is transferred, with the upper 16 bits to the tgr1a register and the lower 16 bits to the tgr2a register. 128 tcnt1 clock tcnt2 clock tioc1a, tioc2a tcnt1 h'03a1 h'ffff h'0000 h'0001 h'03a2 tcnt2 tgr1a h'03a2 tgr2a h'0000 figure 8.22 cascade connection operation example (input capture) 8.4.6 pwm mode pwm mode outputs the various pwm waveforms from output pins. output levels of 0 output, 1 output, or toggle output can be selected as the output level for the compare-match of each tgr. a period can be set for a register by using the tgr compare-match as a counter clear source. all five channels can be independently set to pwm mode. synchronous operation is also possible. there are two pwm modes: ? pwm mode 1 generates pwm output using the tgra and tgrb registers, and tgrc and tgrd registers as pairs. the initial output values are those established in the tgra and tgrc registers. when the values set in tgr registers being used as a pair are equal, output values will not change even if a compare-match occurs. a maximum of 4-phase pwm output is possible for pwm mode 1. ? pwm mode 2 generates pwm output using one tgr register as a period register and another as a duty cycle register. the output value of each pin upon a counter clear is the initial value established by the tior register. when the values set in the period register and duty register are equal, output values will not change even if a compare-match occurs. 129 table 8.7 lists the combinations of pwm output pins and registers. table 8.7 combinations of pwm output pins and registers output pin channel register pwm mode 1 pwm mode 2 0 (ab pair) tgr0a tgr0b tioc0a tioc 0a tioc 0b 0 (cd pair) tgr0c tgr0d tioc0c tioc 0c 1 tgr1a tgr1b tioc1a tioc 1a tioc 1b 2 tgr2a tgr2b tioc2a tioc 2a tioc 2b note: pwm output of the period setting tgr is not possible in pwm mode 2. procedure for selecting the pwm mode (figure 8.23): 1. set bits tpsc2?psc0 in the tcr to select the counter clock source. at the same time, set bits ckeg1 and ckeg0 in the tcr to select the desired edge of the input clock. 2. set bits cclr2 to cclr0 in the tcr to select the tgr to be used as a counter clear source. 3. set the period in the tgr selected in step 2, and the duty cycle in another tgr. 4. using the timer i/o control register (tior), set the tgr selected in step 3 to act as an output compare register, and select the initial value and output value. 5. set the md3?d 0 bits in tmdr to select the pwm mode. 6. set the cst bit in the tstr to 1 to let the tcnt start counting. 130 (1) (2) (3) (4) (5) (6) pwm mode select counter clock select waveform output level set tgr select pwm mode start counting pwm mode select counter clear source figure 8.23 procedure for selecting the pwm mode pwm mode operation examples?wm mode 1 (figure 8.24): a tgra register compare- match is used as a tcnt counter clear source, the tgra register initial output value and output compare output value are both 0, and the tgrb register output compare output value is a 1. in this example, the value established in the tgra register becomes the period and the value established in the tgrb register becomes the duty cycle. counter cleared by tgra compare match tcnt value tgra tgrb h'0000 tioca time figure 8.24 pwm mode operation example (mode 1) 131 pwm mode operation examples?wm mode 2 (figure 8.25): channels 0 and 1 are set for synchronous operation, tgr1b register compare-match is used as a tcnt counter clear source, the other tgr register initial output value is 0 and output compare output value is 1, and a 3-phase pwm waveform is output. in this example, the value established in the tgr1b register becomes the period and the value established in the other tgr register becomes the duty cycle. tcntvalue counter cleared on tgr1b compare match tgr0c tgr0a tgr1b tgr1a h'0000 tioc0a tioc0c tioc1a time figure 8.25 pwm mode operation example (mode 2) 0% duty cycle: figure 8.26 shows an example of a 0% duty cycle pwm waveform output in pwm mode. tgra tcnt value tgrb rewrite tgrb time 0% duty cycle tgrb rewrite tgrb rewrite ticca figure 8.26 pwm mode operation example (0% duty cycle) 132 100% duty cycle: figure 8.27 shows an example of a 100% duty cycle pwm waveform output in pwm mode. in pwm mode, when setting cycle = duty cycle the output waveform does not change, nor is there a change of waveform for the first pulse immediately after clearing the counter. tgra tcnt value tgrb rewrite tgrb time time 100% duty cycle output does not change if period register and duty cycle register compare matches occur simultaneously output does not change if period register and duty cycle register compare matches occur simultaneously tgrb rewrite tgrb rewrite tgra tcnt value tgrb rewrite tgrb tgrb rewrite 100% duty cycle 0% duty cycle tgrb rewrite figure 8.27 pwm mode operation example (100% duty cycle) 133 8.5 interrupts 8.5.1 interrupt sources and priority ranking the mtu has two interrupt sources: tgr register compare-match/input captures, tcnt counter overflows. because each of these three types of interrupts are allocated its own dedicated status flag and enable/disable bit, the issuing of interrupt request signals to the interrupt controller can be independently enabled or disabled. when an interrupt source is generated, the corresponding status flag in the timer status register (tsr) is set to 1. if the corresponding enable/disable bit in the timer input enable register (tier) is set to 1 at this time, the mtu makes an interrupt request of the interrupt controller. the interrupt request is canceled by clearing the status flag to 0. the channel priority order can be changed with the interrupt controller. the priority ranking within a channel is fixed. for more information, see section 6, interrupt controller. table 8.8 lists the mtu interrupt sources. input capture/compare match interrupts: if the tgie bit of the timer input enable register (tier) is already set to 1 when the tgf flag in the timer status register (tsr) is set to 1 by a tgr register input capture/compare-match of any channel, an interrupt request is sent to the interrupt controller. the interrupt request is canceled by clearing the tgf flag to 0. the mtu has 8 input capture/compare-match interrupts; four each for channel 0, and two each for channels 1 and 2. overflow interrupts: if the tciev bit of the tier is already set to 1 when the tcfv flag in the tsr is set to 1 by a tcnt counter overflow of any channel, an interrupt request is sent to the interrupt controller. the interrupt request is canceled by clearing the tcfv flag to 0. the mtu has three overflow interrupts, one for each channel. 134 table 8.8 mtu interrupt sources channel interrupt source description priority* 0 tgi0a tgr0a input capture/compare-match high tgi0b tgr0b input capture/compare-match tgi0c tgr0c input capture/compare-match tgi0d tgr0d input capture/compare-match tci0v tcnt0 overflow 1 tgi1a tgr1a input capture/compare-match tgi1b tgr1b input capture/compare-match tci1v tcnt1 overflow 2 tgi2a tgr2a input capture/compare-match tgi2b tgr2b input capture/compare-match tci2v tcnt2 overflow tci2u tcnt2 underflow low note: indicates the initial status following reset. the ranking of channels can be altered using the interrupt controller. 8.5.2 a/d converter activation the tgra register input capture/compare-match of any channel can be used to activate the on- chip a/d converter. if the ttge bit of the tier is already set to 1 when the tgfa flag in the tsr is set to 1 by a tgra register input capture/compare-match of any of the channels, an a/d conversion start request is sent to the a/d converter. if the mtu conversion start trigger is selected at such a time on the a/d converter side when this happens, the a/d conversion starts. the mtu has 3 tgra register input capture/compare-match interrupts, one for each channel, that can be used as a/d converter activation sources. 135 8.6 operation timing 8.6.1 input/output timing tcnt count timing: count timing for the tcnt counter with internal clock operation is shown in figure 8.28. tcnt input clock internal clock tcnt f falling edge falling edge rising edge n ?1 n n + 1 n + 2 figure 8.28 tcnt count timing during internal clock operation output compare output timing: the compare-match signal is generated at the final state of tcnt and tgr matching. when a compare-match signal is issued, the output value set in tior or tocr is output to the output compare output pin (tioc pin). after tcnt and tgr matching, a compare-match signal is not issued until immediately before the tcnt input clock. output compare output timing (normal mode and pwm mode) is shown in figure 8.29. 136 tcnt input clock tioc pin compare- match signal tcnt tgr f n n n + 1 figure 8.29 output compare output timing (normal mode/pwm mode) input capture signal timing: figure 8.30 illustrates input capture timing. input capture input input capture signal tcnt tgr f n n + 2 n n + 2 n + 1 rising edge falling edge figure 8.30 input capture input signal timing 137 counter clearing timing due to compare-match/input capture: timing for counter clearing due to compare-match is shown in figure 8.31. figure 8.32 shows the timing for counter clearing due to input capture. compare- match signal f counter clear signal tcnt tgr n n h'0000 figure 8.31 counter clearing timing (compare-match) input capture signal f counter clear signal tcnt tgr n n h'0000 figure 8.32 counter clearing timing (input capture) 138 buffer operation timing: compare-match buffer operation timing is shown in figure 8.33. figure 8.34 shows input capture buffer operation timing. tcnt f compare- match buffer signal tgra, tgrb tgrc, tgrd n n + 1 nn n compare- match signal figure 8.33 buffer operation timing (compare-match) tcnt f input capture signal buffer tgra, tgrb tgrc, tgrd n n + 1 nn n n + 1 n input capture signal figure 8.34 buffer operation timing (input capture) 139 8.6.2 interrupt signal timing setting tgf flag timing during compare-match: figure 8.35 shows timing for the tgf flag of the timer status register (tsr) due to compare-match, as well as tgi interrupt request signal timing. compare- match signal tcnt tcnt input clock f tgr tgf flag tgi interrupt n n + 1 n figure 8.35 tgi interrupt timing (compare match) 140 setting tgf flag timing during input capture: figure 8.36 shows timing for the tgf flag of the timer status register (tsr) due to input capture, as well as tgi interrupt request signal timing. input capture signal tcnt f tgr tgf flag tgi interrupt n n figure 8.36 tgi interrupt timing (input capture) setting timing for overflow flag (tcfv): figure 8.37 shows timing for the tcfv flag of the timer status register (tsr) due to overflow, as well as tciv interrupt request signal timing. overflow signal tcnt (overflow) tcnt input clock f tcfv flag tciv interrupt h'ffff h'0000 figure 8.37 tciv interrupt setting timing 141 status flag clearing timing: the status flag is cleared when the cpu reads a 1 status followed by a 0 write. figure 8.38 shows the timing for status flag clearing by the cpu. status flag interrupt request signal address write signal f t 1 t 2 tsr write cycle tsr address figure 8.38 timing of status flag clearing by the cpu 8.7 notes and precautions this section describes contention and other matters requiring special attention during mtu operations. note on cycle setting: when setting a counter clearing by compare-match, clearing is done in the final state when tcnt matches the tgr value (update timing for count value on tcnt match). the actual number of states set in the counter is given by the following equation: f = (n + 1) f (f: counter frequency, f : operating frequency, n: value set in the tgr) contention between tcnt write and clear: if a counter clear signal is issued in the t 2 state during the tcnt write cycle, tcnt clearing has priority, and tcnt write is not conducted (figure 8.39). 142 counter clear signal tcnt address write signal f t 1 t 2 tcnt write cycle tcnt address n h'0000 figure 8.39 tcnt write and clear contention contention between tcnt write and increment: if a count-up signal is issued in the t 2 state during the tcnt write cycle, tcnt write has priority, and the counter is not incremented (figure 8.40). tcnt input clock tcnt address write signal f t 1 t 2 tcnt write cycle tcnt write data tcnt address m n figure 8.40 tcnt write and increment contention 143 contention between buffer register write and compare match: if a compare-match occurs in the t 2 state of the tgr write cycle, data is transferred by the buffer operation from the buffer register to the tgr. on channel 0, the data to be transferred is that after the write (figure 8.41). buffer register compare match signal compare match buffer signal address write signal tgr f t 1 t 2 tgr write cycle buffer register address nm buffer register write data m figure 8.41 tgr write and compare-match contention (channel 0) 144 contention between tgr read and input capture: if an input capture signal is issued in the t 1 state of the tgr read cycle, the read data is that after input capture transfer (figure 8.42). tgr input capture signal internal data bus address read signal f t 1 t 2 tgr read cycle tgr address m xm figure 8.42 tgr read and input capture contention 145 contention between tgr write and input capture: if an input capture signal is issued in the t 2 state of the tgr read cycle, input capture has priority, and tgr write does not occur (figure 8.43). tgr input capture signal tcnt address write signal f t 1 t 2 tgr write cycle tgr address m m figure 8.43 tgr write and input capture contention 146 contention between buffer register write and input capture: if an input capture signal is issued in the t 2 state of the buffer write cycle, write to the buffer register does not occur, and buffer operation takes priority (figure 8.44). tgr input capture signal tcnt address write signal buffer re g ister f t 1 t 2 buffer register write cycle buffer register address n mn m figure 8.44 buffer register write and input capture contention 147 contention between tgr write and compare match: if a compare-match occurs in the t 2 state of the tgr write cycle, data is written to the tgr and a compare-match signal is issued (figure 8.45). tgr compare match signal tcnt address write signal f t 1 t 2 tgr write cycle tgr address n n + 1 m n tgr write data figure 8.45 tgr write and compare match contention tcnt2 write and overflow contention in cascade connection: with timer counters tcnt1 and tcnt2 in a cascade connection, when a contention occurs during tcnt1 count (during a tcnt2 overflow) in the t 2 state of the tcnt2 write cycle, the write to tcnt2 is conducted, and the tcnt1 count signal is prohibited. at this point, if there is match with tgr1a and the tcnt1 value, a compare signal is issued. when the tcnt1 count clock is selected as the channel 0 input capture source, tgr0a and tgr0c operate as input capture registers. when tgr0c compare- match/input capture is selected as the tgr1b input capture source, tgr1b operates as an input capture register. the timing is shown in figure 8.46. for cascade connections, be sure to synchronize settings for channels 1 and 2 when setting tcnt clearing. 148 t1 t2 h'fffe h'ffff n n + 1 h'ffff m m n p qp m disabled tcnt2 write data tcnt2 address tcnt write cycle f address write signal tcnt2 tgr2a? ch2 compare- match signal a/b tcnt1 input clock tcnt1 tgr1a ch1 compare- match signal a tgr1b ch1 inputcapture signal b tcnt0 tgr0a? ch0 input capture signal a, c figure 8.46 tcnt2 write and overflow contention with cascade connection 149 contention between overflow and counter clearing: if overflow and counter clearing occur simultaneously, the tcfv flag in tsr is not set and tcnt clearing takes precedence. figure 8.47 shows the operation timing when a tgr compare-match is specified as the clearing source, and h'ffff is set in tgr. tcnt input clock tcnt counter clear signal tgf flag tcfv flag h'ffff h'0000 disabled figure 8.47 contention between overflow and counter clearing contention between tcnt write and overflow: if there is an up-count in the t2 state of a tcnt write cycle, and overflow occurs, the tcnt write takes precedence and the tcfv flag in tsr is not set . figure 8.48 shows the operation timing in this case. 150 address write signal tcnt input clock tcnt tcfv flag h'ffff n tcnt write data disabled tcnt write cycle t1 t2 tcnt address figure 8.48 contention between tcnt write and overflow 8.8 mtu output pin initialization 8.8.1 operating modes the mtu has the following three operating modes. waveform output is possible in all of these modes. ? normal mode (channels 0 to 2) ? pwm mode 1 (channels 0 to 2) ? pwm mode 2 (channels 0 to 2) the mtu output pin initialization method for each of these modes is described in this section. 151 8.8.2 reset start operation the mtu output pins (tioc*) are initialized low by a reset and in standby mode. since mtu pin function selection is performed by the pin function controller (pfc), when the pfc is set, the mtu pin states at that point are output to the ports. when mtu output is selected by the pfc immediately after a reset, the mtu output initial level, low, is output directly at the port. when the active level is low, the system will operate at this point, and therefore the pfc setting should be made after initialization of the mtu output pins is completed. note: * represents the channel number and port symbol. 8.8.3 operation in case of re-setting due to error during operation, etc. if an error occurs during mtu operation, mtu output should be cut by the system. cutoff is performed by switching the pin output to port output with the pfc and outputting the inverse of the active level. the pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. the mtu has three operating modes, as stated above. there are thus 9 mode transition combinations. possible mode transition combinations are shown in table 8.9. table 8.9 mode transition combinations after before normal pwm1 pwm2 normal (1) (2) (3) pwm1 (4) (5) (6) pwm2 (7) (8) (9) legend: normal: normal mode pwm1: pwm1 mode pwm2: pwm2 mode the above abbreviations are used in some places in the following descriptions. 152 8.8.4 overview of initialization procedures and mode transitions in case of error during operation, etc. ? when making a transition to a mode (normal, pwm1, pwm2) in which the pin output level is selected by the timer i/o control register (tior) setting, initialize the pins by means of a tior setting. ? in pwm mode 1, since a waveform is not output to the tioc*b pin, setting tior will not initialize the pins. if initialization is required, carry it out in normal mode, then switch to pwm mode 1. ? in pwm mode 2, since a waveform is not output to the cycle register pin, setting tior will not initialize the pins. if initialization is required, carry it out in normal mode, then switch to pwm mode 2. ? in normal mode or pwm mode 2, if tgrc and tgrd operate as buffer registers, setting tior will not initialize the buffer register pins. if initialization is required, clear buffer mode, carry out initialization, then set buffer mode again. ? in pwm mode 1, if either tgrc or tgrd operates as a buffer register, setting tior will not initialize the tgrc pin. to initialize the tgrc pin, clear buffer mode, carry out initialization, then set buffer mode again. note: an asterisk in this section represents the channel number. pin initialization procedures are described below for the numbered combinations in table 8.9. the active level is assumed to be low. 153 (1) operation when error occurs during normal mode operation, and operation is restarted in normal mode: figure 8.49 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (normal) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output n = 0, 2, 4?, 12?4 tioc*a tioc*b port output pen pen z z figure 8.49 error occurrence in normal mode, recovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. after a reset, the tmdr setting is for normal mode. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. not necessary when restarting in normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 154 (2) operation when error occurs during normal mode operation, and operation is restarted in pwm mode 1: figure 8.50 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (normal) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output n = 0, 2, 4?, 12?4 tioc*a tioc*b port output pen pen z z ?not initialized (to*b) figure 8.50 error occurrence in normal mode, recovery in pwm mode 1 1 to 9 are the same as in figure 8.49. 10. set pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the to*b side is not initialized. if initialization is required, initialize in normal mode, then switch to pwm mode 1.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 155 (3) operation when error occurs during normal mode operation, and operation is restarted in pwm mode 2: figure 8.51 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (normal) 4 pfc (mtu) 3 tior ("1"init "0"out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output n = 0, 2, 4?, 12?4 tioc*a tioc*b port output pen pen z z ?not initialized (cycle register) figure 8.51 error occurrence in normal mode, recovery in pwm mode 2 1 to 9 are the same as in figure 8.49. 10. set pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized. if initialization is required, initialize in normal mode, then switch to pwm mode 2.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 156 (4) operation when error occurs during pwm mode 1 operation, and operation is restarted in normal mode: figure 8.52 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (pwm1) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc*a tioc*b port output pen pen z z ?not initialized (tioc*b) n = 0, 2, 4?, 12?4 figure 8.52 error occurrence in pwm mode 1, recovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. set pwm mode 1. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence. in pwm mode 1, the tioc*b side is not initialized.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. set normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 157 (5) operation when error occurs during pwm mode 1 operation, and operation is restarted in pwm mode 1: figure 8.53 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (pwm1) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc*a tioc*b port output pen pen z z ?not initialized (tioc*b) ?not initialized (tioc*b) n = 0, 2, 4?, 12?4 figure 8.53 error occurrence in pwm mode 1, recovery in pwm mode 1 1 to 9 are the same as in figure 8.52. 10. not necessary when restarting in pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 158 (6) operation when rrror occurs during pwm mode 1 operation, and operation is restarted in pwm mode 2: figure 8.54 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (pwm1) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc*a tioc*b port output pen pen z z ?not initialized (tioc*b) ?not initialized (cycle register) n = 0, 2, 4?, 12?4 figure 8.54 error occurrence in pwm mode 1, recovery in pwm mode 2 1 to 9 are the same as in figure 8.52. 10. set pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 159 (7) operation when error occurs during pwm mode 2 operation, and operation is restarted in normal mode: figure 8.55 shows an explanatory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc*a tioc*b port output pen pen z z ?not initialized (cycle register) n = 0, 2, 4?, 12?4 figure 8.55 error occurrence in pwm mode 2, recovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. set pwm mode 2. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence. in pwm mode 2, the cycle register pins are not initialized. in the example, tioc*a is the cycle register.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. set normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 160 (8) operation when error occurs during pwm mode 2 operation, and operation is restarted in pwm mode 1: figure 8.56 shows an explanatory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc*a tioc*b port output pe* pe* z z ?not initialized (tioc*b) ?not initialized (cycle register) n = 0, 2, 4?, 12?4 figure 8.56 error occurrence in pwm mode 2, recovery in pwm mode 1 1 to 9 are the same as in figure 8.55. 10. set pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 161 (9) operation when error occurs during pwm mode 2 operation, and operation is restarted in pwm mode 2: figure 8.57 shows an explanatory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc*a tioc*b port output pen pen z z ?not initialized (cycle register) ?not initialized (cycle register) n = 0, 2, 4?, 12?4 figure 8.57 error occurrence in pwm mode 2, recovery in pwm mode 2 1 to 9 are the same as in figure 8.55. 10. not necessary when restarting in pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 163 section 9 8-bit timer 1 (tim1) 9.1 overview 8-bit timer 1 (tim1) is a single-channel interval timer that generates an interval timer interrupt each time the counter overflows. 9.1.1 features ? 8-bit interval timer ? generates interval timer interrupts an interval timer interrupt is generated each time the counter overflows. ? selection of eight counter input clock sources 164 9.1.2 block diagram figure 9.1 shows a block diagram of 8-bit timer 1 (tim1). interrupt control overflow clock clock selection iti (interrupt request signal) t1cnt t1csr module bus internal clock sources internal bus bus interface f /2 f /64 f /128 f /256 f /512 f /1024 f /4096 f /8192 8-bit timer 1 t1csr: t1cnt: timer 1 control/status register timer 1 counter figure 9.1 block diagram of 8-bit timer 1 165 9.1.3 register configuration 8-bit timer 1 (tim1) has two registers, as shown in table 9.1. these registers perform clock selection and other functions. table 9.1 8-bit timer 1 registers address name abbreviation r/w initial value write* 1 read* 2 timer 1 control/ status register t1csr r/(w)* 3 h18 h'ffff8610 h'ffff8610 timer 1 counter t1cnt r/w h'00 h'ffff8611 notes: 1. use word-length writes. byte and longword writes cannot be used. 2. use byte-length reads. a word or longword read will not return the correct value. 3. only 0 can be written in bit 7, to clear the flag. 9.2 register descriptions 9.2.1 timer 1 counter (t1cnt) the timer 1 counter (t1cnt) is an 8-bit readable/writable* up-counter. when the timer enable bit (tme) is set to 1 in the timer 1 control/status register (t1csr), t1cnt starts incrementing on the internal clock selected by bits cks2?ks0 in t1csr. when the t1cnt value overflows (from h'ff to h'00), an interval timer interrupt (iti) is generated. t1cnt is initialized to h'00 by a hardware reset or when the tme bit is 0. note: the method for writing to t1cnt is different from that for general registers to prevent inadvertent overwriting. for details, see section 9.2.3, notes on register access. bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 166 9.2.2 timer 1 control/status register (t1csr) the timer 1 control/status register (t1csr) is an 8-bit readable/writable* register that selects the clock to be input to the timer 1 counter (t1cnt) and the timer mode. bits 7, 5, and 2 through 0 are initialized to 0 by a power-on reset. note: the method for writing to t1csr is different from that for general registers to prevent inadvertent overwriting. for details, see section 9.2.3, notes on register access. bit: 7 6 5 4 3 2 1 0 ovf tme cks2 cks1 cks0 initial value: 0 0 0 1 1 0 0 0 r/w: r/(w)* r r/w r r r/w r/w r/w ? bit 7?verflow flag (ovf): indicates that t1cnt has overflowed from h'ff to h'00. bit 7: ovf description 0 no t1cnt overflow (initial value) [clearing condition] cleared by reading ovf then writing 0 in ovf 1 [setting condition] set when t1cnt overflows ? bit 6?eserved: this bit always reads 0 and must only be written with 0. ? bit 5?imer enable (tme): selects whether tcnt runs or is halted. bit 5: tme description 0 timer disabled: t1cnt is initialized to h'00 and halted (initial value) 1 timer enabled: t1cnt starts counting, and an interrupt is generated when t1cnt overflows ? bits 4 and 3?eserved: these bits always read 1 and must only be written with 1. ? bits 2 to 0?lock select 2 to 0 (cks2?ks0): these bits select one of eight internal clock sources, obtained by dividing the system clock ( f ), for input to t1cnt. 167 bit 2: bit 1: bit 0: description cks2 cks1 cks0 clock overflow period* (when f = 20.0 mhz) 000 f /2 (initial value) 25.6 m s 1 f /64 819.2 m s 10 f /128 1.6384 ms 1 f /256 3.2768 ms 100 f /512 6.5536 ms 1 f /1024 13.1072 ms 10 f /4096 52.4288 ms 1 f /8192 104.8576 ms note: the overflow period is the time from when t1cnt starts counting up from h'00 until overflow occurs. 9.2.3 notes on register access the method for writing to the timer 1 counter (t1cnt) and the timer 1 control/status register (t1csr) is different from that for general registers to prevent inadvertent overwriting. the procedures for writing to and reading these registers are given below. writing to t1cnt and t1csr: these registers must be written to with a word transfer instruction. they cannot be written to with a byte instruction. t1cnt and t1csr both have the same write address. for a write to t1cnt, the upper byte of the written word must contain h'5a and the lower byte must contain the write data. for a write to t1csr, the upper byte of the written word must contain h'a5 and the lower byte must contain the write data. this transfers the write data from the lower byte to t1cnt or t1csr. (see figure 9.2). 15 8 7 0 15 8 7 0 h'5a h'a5 write data write data t1cnt write t1csr write address: h'ffff8610 address: h'ffff8610 figure 9.2 writing to t1cnt and t1csr 168 reading t1cnt and t1csr: these registers are read in the same way as other registers. the read addresses are h'ffff8610 for t1csr and h'ffff8611 for t1cnt. a byte transfer instruction must be used to read these registers. 9.3 operation 9.3.1 interval timer operation to use the interval timer function, set the tme bit to 1 in the timer 1 control/status register (t1csr). an interval timer interrupt (iti) is generated each time the timer 1 counter (t1cnt) overflows, as shown in figure 9.3. this function can be used to generate interrupts at regular intervals. t1cnt value h'ff h'00 overflow tme = 1 iti iti iti iti time iti: interval timer interrupt request generation overflow overflow overflow figure 9.3 interval timer operation 169 9.3.2 timing of overflow flag (ovf) setting when the timer 1 counter (t1cnt) overflows, the ovf bit is set to 1 in the timer 1 serial control register (t1csr) and, at the same time, an interval timer interrupt (iti) is requested. the timing is shown in figure 9.4. ck t1cnt overflow signal (internal signal) ovf h'ff h'00 figure 9.4 timing of overflow flag (ovf) setting 170 9.4 usage notes 9.4.1 contention between timer 1 counter (tcnt) write and increment if a timer 1 counter clock pulse is generated during the t3 state of a timer 1 counter (tcnt) write cycle, the data write to t1cnt takes priority and the timer counter is not incremented. figure 9.5 shows the operation in this case. t1 t2 t3 ck address t1cnt write cycle t1cnt address internal write signal t1cnt input clock pulse t1cnt n m counter write data figure 9.5 contention between t1cnt write and increment 9.4.2 rewriting bits cks2 to cks0 if bits cks2 to cks0 in the timer 1 control/status register (t1csr) are rewritten while 8-bit timer 1 (tim1) is running, the timer counter may not increment correctly. tim1 must therefore be stopped (by clearing the tme bit to 0) before rewriting bits cks2 to cks0. 171 section 10 8-bit timer 2 (tim2) 10.1 overview 8-bit timer 2 (tim2) is a single-channel interval timer that generates compare match interrupts. 10.1.1 features ? 8-bit interval timer ? generates compare match interrupts a compare match interrupt is generated by a counter compare match. ? selection of seven counter input clock sources 172 10.1.2 block diagram figure 10.1 shows a block diagram of 8-bit timer 2 (tim2). interrupt control clock clock selection cmi (interrupt request signal) comparator t2cnt t2cor t2csr module bus internal bus bus interface f /2 f /8 f /32 f /128 f /512 f /2048 f /4096 8-bit timer 2 t2csr: t2cnt: t2cor: timer 2 control/status register timer 2 counter timer 2 constant register figure 10.1 block diagram of 8-bit timer 2 10.1.3 register configuration 8-bit timer 2 (tim2) has three registers for compare match cycle setting, clock selection, and other functions. the register configuration is shown in table 10.1. all the registers are 16 bits in size, and are initialized by a power-on reset. 173 table 10.1 8-bit timer 2 registers name abbreviation r/w initial value address access size timer 2 control/status register t2csr r/w h'0000 h'ffff862c 8, 16, 32 timer 2 counter t2cnt r/w h'0000 h'ffff862e 8, 16, 32 timer 2 constant register t2cor r/w h'0000 h'ffff8630 8, 16 10.2 register descriptions 10.2.1 timer 2 control/status register (t2csr) the timer 2 control/status register (t2csr) is a 16-bit readable/writable* register that selects the clock to be input to the timer 2 counter (t2cnt) and controls compare match interrupts (cmi). t2csr is initialized to h'0000 by a power-on reset. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 cmf cmie cks2 cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r r ? bits 15 to 7?eserved: these bits always read 0 and must only be written with 0. ? bit 6?ompare match flag (cmf): status flag that indicates a match between the values of t2cnt and t2cor. the setting and clearing conditions for this flag are shown below. bit 6: cmf description 0 [clearing condition] cleared by reading t2csr when cmf = 1, then writing 0 in cmf (initial value) 1 [setting condition] set when t2cnt = t2cor* note: when t2cnt and t2cor still contain their initial values (when the initial values have not been changed or when the t2cnt value has not been incremented), cmf is not set even though the t2cnt and t2cor values are the same (h'0000). 174 ? bit 5?ompare match interrupt enable (cmie): enables or disables interrupt requests initiated by the cmf flag when set to 1 in t2csr. bit 5: cmie description 0 interrupt request by cmf flag disabled (initial value) 1 interrupt request by cmf flag enabled ? bits 4 to 2?lock select 2 to 0 (cks2?ks0): these bits select one of seven internal clock sources, obtained by dividing the system clock ( f ), for input to t2cnt. bit 4: cks2 bit 3: cks1 bit 2: cks0 description 0 0 0 up-count stopped (initial value) 1 f /2 10 f /8 1 f /32 100 f /128 1 f /512 10 f /2048 1 f /4096 ? bits 1 and 0?eserved: these bits always read 0 and must only be written with 0. 10.2.2 timer 2 counter (t2cnt) the timer 2 counter (t2cnt) is a 16-bit readable/writable register used as an 8-bit up-counter. t2cnt increments on the internal clock selected by bits cks2?ks0 in t2csr. the t2cnt value can be read or written by the cpu at all times. when the t2cnt value matches the value in the timer 2 constant register (t2cor), t2cnt is cleared to h'0000 and the cmf flag is set to 1 in t2csr. if the cmie bit in t2csr is set to 1 at this time, a compare match interrupt (cmi) is generated. bits 15 to 8 are reserved and have no counter function. these bits always read 0 and must only be written with 0. t2cnt is initialized to h'0000 by a power-on reset 175 bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 10.2.3 timer 2 constant register (t2cor) the timer 2 constant register (t2cor) is a 16-bit readable/writable register that is used to set the t2cnt compare match cycle. the values in t2cor and t2cnt are continually compared, and when the values match the cmf flag is set in t2csr and t2cnt is cleared to 0. if the cmie bit in t2csr is set to 1, an interrupt request is sent to the interrupt controller in response to the match signal. the interrupt request is output continuously until the cmf flag in t2csr is cleared. bits 15 to 8 are reserved and are not used in the cycle setting. these bits always read 0. t2cor is initialized to h'0000 by a power-on reset. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 176 10.3 operation 10.3.1 cyclic count operation when a clock is selected with bits cks2?ks0 in the t2csr register, the t2cnt counter starts incrementing on the selected clock. when the t2cnt counter value matches the value in the timer 2 constant register (t2cor), the t2cnt counter is cleared to h'00, and the cmf flag is set to 1 in the t2csr register. if the cmie bit in t2csr is set to 1 at this time, a compare match interrupt (cmi) is requested. the t2cnt counter then starts incrementing again from h'00. the compare match counter operation is shown in figure 10.2. t2cnt value t2cor h'00 counter cleared by t2cor compare match time figure 10.2 counter operation 10.3.2 t2cnt count timing any of seven internal clocks ( f /2, f /8, f /32, f /128, f /512, f /2048, or f /4096) divided from the system clock (ck) can be selected with bits cks2?ks0 in t2csr. the count timing is shown in figure 10.3. ck internal clock t2cnt input clock t2cnt n ?1 n n + 1 figure 10.3 count timing 177 10.4 interrupts 10.4.1 interrupt source when interrupt request flag cmf is set to 1, and interrupt enable bit cmie is also 1, the corresponding interrupt request is output. 10.4.2 timing of compare match flag setting the cmf bit in the t2csr register is set to 1 by the compare match signal generated when the t2cor register and t2cnt counter values match. the compare match signal is generated in the last state in which the match is true (when the value at which the t2cnt counter match occurred is about to be updated). therefore, after a match between the t2cnt counter and the t2cor register, the compare match signal is not generated until the next t2cnt counter input clock pulse. figure 10.4 shows the timing of cmf bit setting. ck t2cnt input clock pulse t2cnt t2cor n0 n compare match signal cmf cmi figure 10.4 timing of cmf setting 178 10.4.3 timing of compare match flag clearing the cmf bit in the t2csr register is cleared by reading the bit when it is set to 1, then writing 0 in it. figure 10.5 shows the timing of cmf bit clearing by the cpu. t1 t2 t2csr write cycle ck cmf figure 10.5 timing of cmf clearing by cpu 179 section 11 compare match timer (cmt) 11.1 overview the SH7011 has an on-chip compare match timer (cmt) configured of 16-bit timers for two channels. the cmt has 16-bit counters and can generate interrupts at set intervals. 11.1.1 features the cmt has the following features: ? four types of counter input clock can be selected ? one of four internal clocks ( f /8, f /32, f /128, f /512) can be selected independently for each channel. ? interrupt sources ? a compare match interrupt can be requested independently for each channel. 180 11.1.2 block diagram figure 11.1 shows a block diagram of the cmt. cm10 control circuit internal bus clock selection control circuit clock selection cmi1 f /8 f /32 f /128 f /512 f /8 f /32 f /128 f /512 cmcsr1 cmcor1 cmcnt1 cmcnt0 cmcor0 comparator cmstr cmcsr0 comparator bus interface module bus cmt cmstr: cmcsr: cmcor: cmcnt: cmi: compare match timer start register compare match timer control/status register compare match timer constant register compare match timer counter compare match interrupt figure 11.1 cmt block diagram 181 11.1.3 register configuration table 11.1 summarizes the cmt register configuration. table 11.1 register configuration channel name abbreviation r/w initial value address access size (bits) shared compare match timer start register cmstr r/w h'0000 h'ffff83d0 8, 16, 32 0 compare match timer control/status register 0 cmcsr0 r/(w)* h'0000 h'ffff83d2 8, 16, 32 compare match timer counter 0 cmcnt0 r/w h'0000 h'ffff83d4 8, 16, 32 compare match timer constant register 0 cmcor0 r/w h'ffff h'ffff83d6 8, 16, 32 1 compare match timer control/status register 1 cmcsr1 r/(w)* h'0000 h'ffff83d8 8, 16, 32 compare match timer counter 1 cmcnt1 r/w h'0000 h'ffff83da 8, 16, 32 compare match timer constant register 1 cmcor1 r/w h'ffff h'ffff83dc 8, 16 note: the only value that can be written to the cmcsr0 and cmcsr1 cmf bits is a 0 to clear the flags. 182 11.2 register descriptions 11.2.1 compare match timer start register (cmstr) the compare match timer start register (cmstr) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (cmcnt). it is initialized to h'0000 by power-on resets. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 str1 str0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w ? bits 15??eserved: these bits always read as 0. the write value should always be 0. ? bit 1?ount start 1 (str1): selects whether to operate or halt compare match timer counter 1. bit 1: str1 description 0 cmcnt1 count operation halted (initial value) 1 cmcnt1 count operation ? bit 0?ount start 0 (str0): selects whether to operate or halt compare match timer counter 0. bit 0: str0 description 0 cmcnt0 count operation halted (initial value) 1 cmcnt0 count operation 183 11.2.2 compare match timer control/status register (cmcsr) the compare match timer control/status register (cmcsr) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock used for incrementation. it is initialized to h'0000 by power-on resets. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 cmf cmie cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/(w)* r/w r r r r r/w r/w note: the only value that can be written is a 0 to clear the flag. ? bits 15? and 5??eserved: these bits always read as 0. the write value should always be 0. ? bit 7?ompare match flag (cmf): this flag indicates whether or not the cmcnt and cmcor values have matched. bit 7: cmf description 0 cmcnt and cmcor values have not matched (initial status) clear condition: write a 0 to cmf after reading a 1 from it 1 cmcnt and cmcor values have matched ? bit 6?ompare match interrupt enable (cmie): selects whether to enable or disable a compare match interrupt (cmi) when the cmcnt and cmcor values have matched (cmf = 1). bit 6: cmie description 0 compare match interrupts (cmi) disabled (initial status) 1 compare match interrupts (cmi) enabled 184 ? bits 1, 0?lock select 1, 0 (cks1, cks0): these bits select the clock input to the cmcnt from among the four internal clocks obtained by dividing the system clock ( f ). when the str bit of the cmstr is set to 1, the cmcnt begins incrementing with the clock selected by cks1 and cks0. bit 1: cks1 bit 0: cks0 description 00 f /8 (initial status) 1 f /32 10 f /128 1 f /512 11.2.3 compare match timer counter (cmcnt) the compare match timer counter (cmcnt) is a 16-bit register used as an upcounter for generating interrupt requests. when an internal clock is selected with the cks1, cks0 bits of the cmcsr register and the str bit of the cmstr is set to 1, the cmcnt begins incrementing with that clock. when the cmcnt value matches that of the compare match timer constant register (cmcor), the cmcnt is cleared to h'0000 and the cmf flag of the cmcsr is set to 1. if the cmie bit of the cmcsr is set to 1 at this time, a compare match interrupt (cmi) is requested. the cmcnt is initialized to h'0000 by power-on resets. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 185 11.2.4 compare match timer constant register (cmcor) the compare match timer constant register (cmcor) is a 16-bit register that sets the compare match period with the cmcnt. the cmcor is initialized to h'ffff by power-on resets. bit: 15 14 13 12 11 10 9 8 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 11.3 operation 11.3.1 period count operation when an internal clock is selected with the cks1, cks0 bits of the cmcsr register and the str bit of the cmstr is set to 1, the cmcnt begins incrementing with the selected clock. when the cmcnt counter value matches that of the compare match constant register (cmcor), the cmcnt counter is cleared to h'0000 and the cmf flag of the cmcsr register is set to 1. if the cmie bit of the cmcsr register is set to 1 at this time, a compare match interrupt (cmi) is requested. the cmcnt counter begins counting up again from h'0000. figure 11.2 shows the compare match counter operation. cmcor h'0000 cmcnt value time counter cleared by cmcor compare match figure 11.2 counter operation 186 11.3.2 cmcnt count timing one of four clocks ( f /8, f /32, f /128, f /512) obtained by dividing the system clock (ck) can be selected by the cks1, cks0 bits of the cmcsr. figure 11.3 shows the timing. ck n ?1 n n + 1 internal clock cmcnt input clock cmcnt figure 11.3 count timing 11.4 interrupts 11.4.1 interrupt sources the cmt has a compare match interrupt for each channel, with independent vector addresses allocated to each of them. the corresponding interrupt request is output when the interrupt request flag cmf is set to 1 and the interrupt enable bit cmie has also been set to 1. when activating cpu interrupts by interrupt request, the priority between the channels can be changed by using the interrupt controller settings. see section 6, interrupt controller, for details. 11.4.2 compare match flag set timing the cmf bit of the cmcsr register is set to 1 by the compare match signal generated when the cmcor register and the cmcnt counter match. the compare match signal is generated upon the final state of the match (timing at which the cmcnt counter matching count value is updated). consequently, after the cmcor register and the cmcnt counter match, a compare match signal will not be generated until a cmcnt counter input clock occurs. figure 11.4 shows the cmf bit set timing. 187 ck cmcnt input clock cmcnt cmcor compare match signal cmf cmi n n 0 figure 11.4 cmf set timing 11.4.3 compare match flag clear timing the cmf bit of the cmcsr register is cleared either by writing a 0 to it after reading a 1. figure 11.5 shows the timing when the cmf bit is cleared by the cpu. t 2 t 1 ck cmf cmcsr write cycle figure 11.5 timing of cmf clear by the cpu 188 11.5 notes on use take care that the contentions described in sections 11.5.1?1.5.3 do not arise during cmt operation. 11.5.1 contention between cmcnt write and compare match if a compare match signal is generated during the t 2 state of the cmcnt counter write cycle, the cmcnt counter clear has priority, so the write to the cmcnt counter is not performed. figure 11.6 shows the timing. t 1 t 2 ck address internal write signal compare match signal cmcnt cmcnt write cycle cmcnt n h'0000 figure 11.6 cmcnt write and compare match contention 189 11.5.2 contention between cmcnt word write and incrementation if an increment occurs during the t 2 state of the cmcnt counter word write cycle, the counter write has priority, so no increment occurs. figure 11.7 shows the timing. cmcnt write data t 1 t 2 ck address internal write signal compare match signal cmcnt cmcnt write cycle cmcnt nm figure 11.7 cmcnt word write and increment contention 190 11.5.3 contention between cmcnt byte write and incrementation if an increment occurs during the t 2 state of the cmcnt byte write cycle, the counter write has priority, so no increment of the write data results on the writing side. the byte data on the side not performing the writing is also not incremented, so the contents are those before the write. figure 11.8 shows the timing when an increment occurs during the t 2 state of the cmcnth write cycle. t 1 t 2 ck address internal write signal cmcnt input clock cmcnth cmcnt write cycle cmcnth n m cmcnth write data x x cmcntl figure 11.8 cmcnt byte write and increment contention 191 section 12 serial communication interface (sci) 12.1 overview the SH7011 has a serial communication interface (sci) with one channel. the sci supports asynchronous serial communication. it also has a multiprocessor communication function for serial communication among two or more processors. 12.1.1 features ? select asynchronous or clock synchronous as the serial communications mode. ? asynchronous mode: serial data communications are synched by start-stop in character units. the sci can communicate with a universal asynchronous receiver/transmitter (uart), an asynchronous communication interface adapter (acia), or any other chip that employs a standard asynchronous serial communication. it can also communicate with two or more other processors using the multiprocessor communication function. there are twelve selectable serial data communication formats. ? data length: seven or eight bits ? stop bit length: one or two bits ? parity: even, odd, or none ? multiprocessor bit: one or none ? receive error detection: parity, overrun, and framing errors ? break detection: by reading the rxd level directly when a framing error occurs ? full duplex communication: the transmitting and receiving sections are independent, so the sci can transmit and receive simultaneously. both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. ? on-chip baud rate generator with selectable bit rates. ? internal transmit/receive clock source: baud rate generator (internal). ? four types of interrupts: transmit-data-empty, transmit-end, receive-data-full, and receive- error interrupts are requested independently. 192 12.1.2 block diagram figure 12.1 shows a block diagram of the sci. parity generation parity check transmit/ receive control baud rate generator clock bus interface internal data bus rxd rdr tdr rsr tsr ssr scr smr brr f f /4 f /16 f /64 tei txi rxi eri : : : : rsr rdr tsr tdr receive shift register receive data register transmit shift register transmit data register : : : : smr scr ssr brr serial mode register serial control register serial status register bit rate register txd sci module data bus figure 12.1 sci block diagram 12.1.3 pin configuration table 12.1 summarizes the sci pins by channel. table 12.1 sci pins pin name abbreviation input/output function receive data pin rxd input sci receive data input transmit data pin txd output sci transmit data output 193 12.1.4 register configuration table 12.2 summarizes the sci internal registers. these registers specify the data format and bit rate, and control the transmitter and receiver sections. table 12.2 registers name abbreviation r/w initial value address access size serial mode register smr r/w h'00 h'ffff81b0 8, 16 bit rate register brr r/w h'ff h'ffff81b1 8, 16 serial control register scr r/w h'00 h'ffff81b2 8, 16 transmit data register tdr r/w h'ff h'ffff81b3 8, 16 serial status register ssr r/(w)* h'84 h'ffff81b4 8, 16 receive data register rdr r h'00 h'ffff81b5 8, 16 note: the only value that can be written is a 0 to clear the flags.. 12.2 register descriptions 12.2.1 receive shift register (rsr) the receive shift register (rsr) receives serial data. data input at the rxd pin is loaded into the rsr in the order received, lsb (bit 0) first, converting the data to parallel form. when one byte has been received, it is automatically transferred to the rdr. the cpu cannot read or write the rsr directly. bit: 7 6 5 4 3 2 1 0 r/w: 194 12.2.2 receive data register (rdr) the receive data register (rdr) stores serial receive data. the sci completes the reception of one byte of serial data by moving the received data from the receive shift register (rsr) into the rdr for storage. the rsr is then ready to receive the next data. this double buffering allows the sci to receive data continuously. the cpu can read but not write the rdr. the rdr is initialized to h'00 by a power-on reset. bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r 12.2.3 transmit shift register (tsr) the transmit shift register (tsr) transmits serial data. the sci loads transmit data from the transmit data register (tdr) into the tsr, then transmits the data serially from the txd pin, lsb (bit 0) first. after transmitting one data byte, the sci automatically loads the next transmit data from the tdr into the tsr and starts transmitting again. if the tdre bit of the ssr is 1, however, the sci does not load the tdr contents into the tsr. the cpu cannot read or write the tsr directly. bit: 7 6 5 4 3 2 1 0 r/w: 12.2.4 transmit data register (tdr) the transmit data register (tdr) is an 8-bit register that stores data for serial transmission. when the sci detects that the transmit shift register (tsr) is empty, it moves transmit data written in the tdr into the tsr and starts serial transmission. continuous serial transmission is possible by writing the next transmit data in the tdr during serial transmission from the tsr. the cpu can always read and write the tdr. the tdr is initialized to h'ff by a power-on reset. 195 bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 12.2.5 serial mode register (smr) the serial mode register (smr) is an 8-bit register that specifies the sci serial communication format and selects the clock source for the baud rate generator. the cpu can always read and write the smr. the smr is initialized to h'00 by a power-on reset. bit: 7 6 5 4 3 2 1 0 chr pe o/ e stop mp cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w ? bit 7?eserved. this bit always reads 0. the write value should always be 0. ? bit 6?haracter length (chr): selects 7-bit or 8-bit data in the asynchronous mode. bit 6: chr description 0 eight-bit data (initial value) 1 seven-bit data. (when 7-bit data is selected, the msb (bit 7) of the transmit data register is not transmitted.) ? bit 5?arity enable (pe): selects whether to add a parity bit to transmit data and to check the parity of receive data. bit 5: pe description 0 parity bit not added or checked (initial value) 1 parity bit added and checked. when pe is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (o/ e ) setting. receive data parity is checked according to the even/odd (o/ e ) mode setting. 196 ? bit 4?arity mode (o/ e ): selects even or odd parity when parity bits are added and checked. the o/ e setting is used only when the parity enable bit (pe) is set to 1 to enable parity addition and check. the o/ e setting is ignored when parity addition and check is disabled. bit 4: o/ e description 0 even parity (initial value). if even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 1 odd parity. if odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. ? bit 3?top bit length (stop): selects one or two bits as the stop bit length. in receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. bit 3: stop description 0 one stop bit (initial value). in transmitting, a single bit of 1 is added at the end of each transmitted character. 1 two stop bits. in transmitting, two bits of 1 are added at the end of each transmitted character. ? bit 2?ultiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, settings of the parity enable (pe) and parity mode (o/ e ) bits are ignored. for the multiprocessor communication function, see section 12.3.3, multiprocessor communication. bit 2: mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected ? bits 1 and 0?lock select 1 and 0 (cks1 and cks0): these bits select the internal clock source of the on-chip baud rate generator. four clock sources are available; f , f /4, f /16, or f /64. for further information on the clock source, bit rate register settings, and baud rate, see section 12.2.8, bit rate register. 197 bit 1: cks1 bit 0: cks0 description 00 f (initial value) 1 f /4 10 f /16 1 f /64 12.2.6 serial control register (scr) the serial control register (scr) operates the sci transmitter/receiver, enables/disables interrupt requests. the cpu can always read and write the scr. the scr is initialized to h'00 by a power- on reset. bit: 7 6 5 4 3 2 1 0 tie rie te re mpie teie initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r r ? bit 7?ransmit interrupt enable (tie): enables or disables the transmit-data-empty interrupt (txi) requested when the transmit data register empty bit (tdre) in the serial status register (ssr) is set to 1 by transfer of serial transmit data from the tdr to the tsr. bit 7: tie description 0 transmit-data-empty interrupt request (txi) is disabled (initial value). the txi interrupt request can be cleared by reading tdre after it has been set to 1, then clearing tdre to 0, or by clearing tie to 0. 1 transmit-data-empty interrupt request (txi) is enabled ? bit 6?eceive interrupt enable (rie): enables or disables the receive-data-full interrupt (rxi) requested when the receive data register full bit (rdrf) in the serial status register (ssr) is set to 1 by transfer of serial receive data from the rsr to the rdr. it also enables or disables receive-error interrupt (eri) requests. bit 6: rie description 0 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are disabled (initial value). rxi and eri interrupt requests can be cleared by reading the rdrf flag or error flag (fer, per, or orer) after it has been set to 1, then clearing the flag to 0, or by clearing rie to 0. 1 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are enabled. 198 ? bit 5?ransmit enable (te): enables or disables the sci serial transmitter. bit 5: te description 0 transmitter disabled (initial value). the transmit data register empty bit (tdre) in the serial status register (ssr) is locked at 1. 1 transmitter enabled. serial transmission starts when the transmit data register empty (tdre) bit in the serial status register (ssr) is cleared to 0 after writing of transmit data into the tdr. select the transmit format in the smr before setting te to 1. ? bit 4?eceive enable (re): enables or disables the sci serial receiver. bit 4: re description 0 receiver disabled (initial value). clearing re to 0 does not affect the receive flags (rdrf, fer, per, orer). these flags retain their previous values. 1 receiver enabled. serial reception starts when a start bit is detected in the asynchronous mode, or synchronous clock input is detected in the clock synchronous mode. select the receive format in the smr before setting re to 1. ? bit 3?ultiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie setting is used only if the multiprocessor mode bit (mp) in the serial mode register (smr) is set to 1 during reception. bit 3: mpie description 0 multiprocessor interrupts are disabled (normal receive operation) (initial value). mpie is cleared when the mpie bit is cleared to 0, or the multiprocessor bit (mpb) is set to 1 in receive data. 1 multiprocessor interrupts are enabled. receive-data-full interrupt requests (rxi), receive-error interrupt requests (eri), and setting of the rdrf, fer, and orer status flags in the serial status register (ssr) are disabled until data with the multiprocessor bit set to 1 is received. the sci does not transfer receive data from the rsr to the rdr, does not detect receive errors, and does not set the rdrf, fer, and orer flags in the serial status register (ssr). when it receives data that includes mpb = 1, mpb is set to 1, and the sci automatically clears mpie to 0, generates rxi and eri interrupts (if the tie and rie bits in the scr are set to 1), and allows the fer and orer bits to be set. 199 ? bit 2?ransmit-end interrupt enable (teie): enables or disables the transmit-end interrupt (tei) requested if tdr does not contain valid transmit data when the msb is transmitted. bit 2: teie description 0 transmit-end interrupt (tei) requests are disabled* (initial value) 1 transmit-end interrupt (tei) requests are enabled.* note: the tei request can be cleared by reading the tdre bit in the serial status register (ssr) after it has been set to 1, then clearing tdre to 0 and clearing the transmit end (tend) bit to 0; or by clearing the teie bit to 0. ? bits 1 and 0?eserved. these bits always read 0. the write value should always be 0. 12.2.7 serial status register (ssr) the serial status register (ssr) is an 8-bit register containing multiprocessor bit values, and status flags that indicate sci operating status. the cpu can always read and write the ssr, but cannot write 1 in the status flags (tdre, rdrf, orer, per, and fer). these flags can be cleared to 0 only if they have first been read (after being set to 1). bits 2 (tend) and 1 (mpb) are read-only bits that cannot be written. the ssr is initialized to h'84 by a power-on reset. bit: 7 6 5 4 3 2 1 0 tdre rdrf orer fer per tend mpb mpbt initial value: 1 0 0 0 0 1 0 0 r/w: r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r r r/w note: the only value that can be written is a 0 to clear the flag. ? bit 7?ransmit data register empty (tdre): indicates that the sci has loaded transmit data from the tdr into the tsr and new serial transmit data can be written in the tdr. bit 7: tdre description 0 tdr contains valid transmit data tdre is cleared to 0 when software reads tdre after it has been set to 1, then writes 0 in tdre 1 tdr does not contain valid transmit data (initial value) tdre is set to 1 when the chip is power-on reset the te bit in the serial control register (scr) is cleared to 0, or tdr contents are loaded into tsr, so new data can be written in tdr 200 ? bit 6?eceive data register full (rdrf): indicates that rdr contains received data. bit 6: rdrf description 0 rdr does not contain valid received data (initial value) rdrf is cleared to 0 when the chip is power-on reset, software reads rdrf after it has been set to 1, then writes 0 in rdrf 1 rdr contains valid received data rdrf is set to 1 when serial data is received normally and transferred from rsr to rdr note: the rdr and rdrf are not affected by detection of receive errors or by clearing of the re bit to 0 in the serial control register. they retain their previous contents. if rdrf is still set to 1 when reception of the next data ends, an overrun error (orer) occurs and the received data is lost. ? bit 5?verrun error (orer): indicates that data reception ended abnormally due to an overrun error. bit 5: orer description 0 receiving is in progress or has ended normally (initial value). clearing the re bit to 0 in the serial control register does not affect the orer bit, which retains its previous value. orer is cleared to 0 when the chip is power-on reset or software reads orer after it has been set to 1, then writes 0 in orer 1 a receive overrun error occurred. rdr continues to hold the data received before the overrun error, so subsequent receive data is lost. serial receiving cannot continue while orer is set to 1. orer is set to 1 if reception of the next serial data ends when rdrf is set to 1 201 ? bit 4?raming error (fer): indicates that data reception ended abnormally due to a framing error. bit 4: fer description 0 receiving is in progress or has ended normally (initial value). clearing the re bit to 0 in the serial control register does not affect the fer bit, which retains its previous value. fer is cleared to 0 when the chip is power-on reset or software reads fer after it has been set to 1, then writes 0 in fer 1 a receive framing error occurred. when the stop bit length is two bits, only the first bit is checked to see if it is a 1. the second stop bit is not checked. when a framing error occurs, the sci transfers the receive data into the rdr but does not set rdrf. serial receiving cannot continue while fer is set to 1. fer is set to 1 if the stop bit at the end of receive data is checked and found to be 0 ? bit 3?arity error (per): indicates that data reception (with parity) ended abnormally due to a parity error. bit 3: per description 0 receiving is in progress or has ended normally (initial value). clearing the re bit to 0 in the serial control register does not affect the per bit, which retains its previous value. per is cleared to 0 when the chip is power-on reset or software reads per after it has been set to 1, then writes 0 in per 1 a receive parity error occurred. when a parity error occurs, the sci transfers the receive data into the rdr but does not set rdrf. serial receiving cannot continue while per is set to 1. per is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (o/ e ) in the serial mode register (smr) 202 ? bit 2?ransmit end (tend): indicates that when the last bit of a serial character was transmitted, the tdr did not contain valid data, so transmission has ended. tend is a read- only bit and cannot be written. bit 2: tend description 0 transmission is in progress tend is cleared to 0 when software reads tdre after it has been set to 1, then writes 0 in tdre 1 end of transmission (initial value) tend is set to 1 when the chip is power-on reset, te is cleared to 0 in the serial control register (scr), or tdre is 1 when the last bit of a one-byte serial character is transmitted. ? bit 1?ultiprocessor bit (mpb): stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving. the mpb is a read-only bit and cannot be written. bit 1: mpb description 0 multiprocessor bit value in receive data is 0 (initial value). if re is cleared to 0 when a multiprocessor format is selected, the mpb retains its previous?alue. 1 multiprocessor bit value in receive data is 1 ? bit 0?ultiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting. bit 0: mpbt description 0 multiprocessor bit value in transmit data is 0 (initial value) 1 multiprocessor bit value in transmit data is 1 203 12.2.8 bit rate register (brr) the bit rate register (brr) is an 8-bit register that, together with the baud rate generator clock source selected by the cks1 and cks0 bits in the serial mode register (smr), determines the serial transmit/receive bit rate. the cpu can always read and write the brr. the brr is initialized to h'ff by a power-on reset. bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 12.3 lists examples of brr settings in the asynchronous mode. table 12.3 bit rates and brr settings f (mhz) bit rate 4 4.9152 6 (bits/s) n n error (%) n n error (%) n n error (%) 110 2 70 0.03 2 86 0.31 2 106 ?.44 150 1 207 0.16 1 255 0.00 2 77 0.16 300 1 103 0.16 1 127 0.00 1 155 0.16 600 0 207 0.16 0 255 0.00 1 77 0.16 1200 0 103 0.16 0 127 0.00 0 155 0.16 2400 0 51 0.16 0 63 0.00 0 77 0.16 4800 0 25 0.16 0 31 0.00 0 38 0.16 9600 0 12 0.16 0 15 0.00 0 19 ?.34 14400 0 8 ?.55 0 10 ?.03 0 12 0.16 19200 0 6 ?.99 0 7 0.00 0 9 ?.34 28800 0 3 8.51 0 4 6.67 0 6 ?.99 31250 0 3 0.00 0 4 ?.70 0 5 0.00 38400 0 2 8.51 0 3 0.00 0 4 ?.34 204 table 12.3 bit rates and brr settings (cont) f (mhz) bit rate 7.3728 8 9.8304 (bits/s) n n error (%) n n error (%) n n error (%) 110 2 130 ?.07 2 141 0.03 2 174 ?.26 150 2 95 0.00 2 103 0.16 2 127 0.00 300 1 191 0.00 1 207 0.16 1 255 0.00 600 1 95 0.00 1 103 0.16 1 127 0.00 1200 0 191 0.00 0 207 0.16 0 255 0.00 2400 0 95 0.00 0 103 0.16 0 127 0.00 4800 0 47 0.00 0 51 0.16 0 63 0.00 9600 0 23 0.00 0 25 0.16 0 31 0.00 14400 0 15 0.00 0 16 2.12 0 20 1.59 19200 0 11 0.00 0 12 0.16 0 15 0.00 28800 0 7 0.00 0 8 ?.55 0 10 ?.03 31250 0 6 5.33 0 7 0.00 0 9 ?.70 38400 0 5 0.00 0 6 ?.99 0 7 0.00 205 table 12.3 bit rates and brr settings (cont) f (mhz) bit rate 10 11.0592 12 (bits/s) n n error (%) n n error (%) n n error (%) 110 2 177 ?.25 2 195 0.19 2 212 0.03 150 2 129 0.16 2 143 0.00 2 155 0.16 300 2 64 0.16 2 71 0.00 2 77 0.16 600 1 129 0.16 1 143 0.00 1 155 0.16 1200 1 64 0.16 1 71 0.00 1 77 0.16 2400 0 129 0.16 0 143 0.00 0 155 0.16 4800 0 64 0.16 0 71 0.00 0 77 0.16 9600 0 32 ?.36 0 35 0.00 0 38 0.16 14400 0 21 ?.36 0 23 0.00 0 25 0.16 19200 0 15 1.73 0 17 0.00 0 19 ?.34 28800 0 10 ?.36 0 11 0.00 0 12 0.16 31250 0 9 0.00 0 10 0.54 0 11 0.00 38400 0 7 1.73 0 8 0.00 0 9 ?.34 206 table 12.3 bit rates and brr settings (cont) f (mhz) bit rate 12.288 14 14.7456 (bits/s) n n error (%) n n error (%) n n error (%) 110 2 217 0.08 2 248 ?.17 3 64 0.70 150 2 159 0.00 2 181 0.16 2 191 0.00 300 2 79 0.00 2 90 0.16 2 95 0.00 600 1 159 0.00 1 181 0.16 1 191 0.00 1200 1 79 0.00 1 90 0.16 1 95 0.00 2400 0 159 0.00 0 181 0.16 0 191 0.00 4800 0 79 0.00 0 90 0.16 0 95 0.00 9600 0 39 0.00 0 45 ?.93 0 47 0.00 14400 0 26 ?.23 0 29 1.27 0 31 0.00 19200 0 19 0.00 0 22 ?.93 0 23 0.00 28800 0 12 2.56 0 14 1.27 0 15 0.00 31250 0 11 2.40 0 13 0.00 0 14 ?.70 38400 0 9 0.00 0 10 3.57 0 11 0.00 207 table 12.3 bit rates and brr settings (cont) f (mhz) bit rate 16 17.2032 18 (bits/s) n n error (%) n n error (%) n n error (%) 110 3 70 0.03 3 75 0.48 3 79 ?.12 150 2 207 0.16 2 223 0.00 2 233 0.16 300 2 103 0.16 2 111 0.00 2 116 0.16 600 1 207 0.16 1 223 0.00 1 233 0.16 1200 1 103 0.16 1 111 0.00 1 116 0.16 2400 0 207 0.16 0 223 0.00 0 233 0.16 4800 0 103 0.16 0 111 0.00 0 116 0.16 9600 0 51 0.16 0 55 0.00 0 58 ?.69 14400 0 34 ?.79 0 36 0.90 0 38 0.16 19200 0 25 0.16 0 27 0.00 0 28 1.02 28800 0 16 2.12 0 18 ?.75 0 19 ?.34 31250 0 15 0.00 0 16 1.20 0 17 0.00 38400 0 12 0.16 0 13 0.00 0 14 ?.34 208 table 12.3 bit rates and brr settings (cont) f (mhz) bit rate 18.432 19.6608 20 (bits/s) n n error (%) n n error (%) n n error (%) 110 3 81 ?.22 3 86 0.31 3 88 ?.25 150 2 239 0.00 2 255 0.00 3 64 0.16 300 2 119 0.00 2 127 0.00 2 129 0.16 600 1 239 0.00 1 255 0.00 2 64 0.16 1200 1 119 0.00 1 127 0.00 1 129 0.16 2400 0 239 0.00 0 255 0.00 1 64 0.16 4800 0 119 0.00 0 127 0.00 0 129 0.16 9600 0 59 0.00 0 63 0.00 0 64 0.16 14400 0 39 0.00 0 42 ?.78 0 42 0.94 19200 0 29 0.00 0 31 0.00 0 32 ?.36 28800 0 19 0.00 0 20 1.59 0 21 ?.36 31250 0 17 2.40 0 19 ?.70 0 19 0.00 38400 0 14 0.00 0 15 0.00 0 15 1.73 209 the brr setting is calculated as follows: n = 64 2 2n? b 10 6 ?1 f b: bit rate (bit/s) n: baud rate generator brr setting (0 n 255) f : operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the following table for the clock sources and value of n.) smr settings n clock cks1 cks2 0 f 00 1 f /4 0 1 2 f /16 1 0 3 f /64 1 1 the bit rate error in asynchronous mode is calculated as follows: error (%) = (n + 1) b 64 2 2n? ?1 100 10 6 f 210 table 12.4 shows the maximum bit rates for various frequencies. table 12.4 maximum bit rates for various frequencies with baud rate generator settings f (mhz) maximum bit rate (bits/s) n n 4 125000 0 0 4.9152 153600 0 0 6 187500 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 11.0592 345600 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 18.432 576000 0 0 19.6608 614400 0 0 20 625000 0 0 211 12.3 operation 12.3.1 overview the sci can perform serial communication in asynchronous mode, in which characters are synchronized individually. the asynchronous mode transmission format is selected in the serial mode register (smr), as shown in table 12.5. asynchronous mode: ? data length is selectable: seven or eight bits. ? parity and multiprocessor bits are selectable, as well as the stop bit length (one or two bits). these selections determine the transmit/receive format and character length. ? in receiving, it is possible to detect framing errors (fer), parity errors (per), overrun errors (orer), and the break state. ? sci clock source: internal clock the sci operates using the on-chip baud rate generator. table 12.5 serial mode register settings and sci communication formats smr settings sci communication format mode bit 6 chr bit 5 pe bit 2 mp bit 3 stop data length parity bit multipro- cessor bit stop bit length asynchronous 0000 8-bit not set not set 1 bit 1 2 bits 1 0 set 1 bit 1 2 bits 1 0 0 7-bit not set 1 bit 1 2 bits 1 0 set 1 bit 1 2 bits asynchronous 0 * 1 0 8-bit not set set 1 bit (multiprocessor * 1 2 bits format) 1 * 0 7-bit 1 bit * 1 2 bits note: asterisks (*) in the table indicate don?-care bits. 212 12.3.2 operation in asynchronous mode in the asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. serial communication is synchronized one character at a time. the transmitting and receiving sections of the sci are independent, so full duplex communication is possible. the transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. figure 12.2 shows the general format of asynchronous serial communication. in asynchronous serial communication, the communication line is normally held in the marking (high) state. the sci monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. one serial character consists of a start bit (low), data (lsb first), parity bit (high or low), and stop bit (high), in that order. when receiving in the asynchronous mode, the sci synchronizes on the falling edge of the start bit. the sci samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. receive data is latched at the center of each bit. 0 d0d1d2d3d4d5d6d7 1 1 0/1 1 1 (lsb) (msb) serial data start bit 1 bit transmit/receive data 7 or 8 bits one unit of communication data (characters or frames) idling (marking state) parity bit stop bit 1 or no bit 1 or 2 bits figure 12.2 data format in asynchronous communication (example: 8-bit data with parity and two stop bits) 213 transmit/receive formats: table 12.6 shows the 12 communication formats that can be selected in the asynchronous mode. the format is selected by settings in the serial mode register (smr). table 12.6 serial communication formats (asynchronous mode) smr bits serial transmit/receive format and frame length bit 6: chr bit 2: mp bit 5: pe bit 3: stop 1 2345678 9 10 11 12 0000 start 8-bit data stop 0001 start 8-bit data stop stop 0010 start 8-bit data p stop 0011 start 8-bit data p stop stop 1000 start 7-bit data stop 1001 start 7-bit data stop stop 1010 start 7-bit data p stop 1011 start 7-bit data p stop stop 0 1 0 start 8-bit data mpb stop 0 1 1 start 8-bit data mpb stop stop 1 1 0 start 7-bit data mpb stop 1 1 1 start 7-bit data mpb stop stop ? don? care bits. note: start: start bit stop: stop bit p: parity bit mpb: multiprocessor bit 214 clock: the sci? transmit/receive clock is an internal clock generated by the on-chip baud rate generator. sci initialization (asynchronous mode): before transmitting or receiving, clear the te and re bits to 0 in the serial control register (scr), then initialize the sci as follows. when changing the operation mode or communication format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets tdre to 1 and initializes the transmit shift register (tsr). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags and receive data register (rdr), which retain their previous contents. figure 12.3 is a sample flowchart for initializing the sci. the procedure is as follows (the steps correspond to the numbers in the flowchart): 1. select the clock source in the serial control register (scr). leave rie, tie, teie, mpie, te and re cleared to 0. 2. select the communication format in the serial mode register (smr). 3. write the value corresponding to the bit rate in the bit rate register (brr). 4. wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scr) to 1. also set rie, tie, teie and mpie as necessary. setting te or re enables the sci to use the txd or rxd pin. the initial states are the marking transmit state, and the idle receive state (waiting for a start bit). 215 initialize clear te and re bits to 0 in scr set cke1 and cke0 bits in scr (te and re bits are 0) select transmit/receive format in smr set value to brr wait set te or re to 1 in scr; set rie, tie, teie, and mpie as necessary 1-bit interval elapsed? end (1) (2) (3) (4) no yes figure 12.3 sample flowchart for sci initialization transmitting serial data (asynchronous mode): figure 12.4 shows a sample flowchart for transmitting serial data. the procedure is as follows (the steps correspond to the numbers in the flowchart): 1. sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr) and clear tdre to 0. 2. to continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in tdr, then clear tdre to 0. 216 start transmitting read tdre bit in ssr read tend bit in ssr tend = 1? end transmission (1) (2) no yes tdre = 1? write transmission data to tdr and clear tdre bit in ssr to 0 all data transmitted? no yes yes no figure 12.4 sample flowchart for transmitting serial data in transmitting serial data, the sci operates as follows: 1. the sci monitors the tdre bit in the ssr. when tdre is cleared to 0, the sci recognizes that the transmit data register (tdr) contains new data, and loads this data from the tdr into the transmit shift register (tsr). 2. after loading the data from the tdr into the tsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) is set to 1 in the scr, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits of data are output, lsb first. c. parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. 217 d. stop bit: one or two 1 bits (stop bits) are output. e. marking: output of 1 bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci loads new data from the tdr into the tsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit to 1 in the ssr, outputs the stop bit, then continues output of 1 bits (marking). if the transmit-end interrupt enable bit (teie) in the scr is set to 1, a transmit-end interrupt (tei) is requested. figure 12.5 shows an example of sci transmit operation. 01 1 1 0/1 0 1 tdre tend parity bit parity bit serial data start bit data stop bit start bit data stop bit idle (marking state) txi interrupt request txi interrupt handler writes data in tdr and clears tdre to 0 tei interrupt request 1 frame d0 d1 d7 d0 d1 d7 0/1 txi interrupt request figure 12.5 sci transmit operation in asynchronous mode (8-bit data with parity and one stop bit) receiving serial data: figures 12.6 show a sample flowchart for receiving serial data. the procedure is as follows (the steps correspond to the numbers in the flowchart). 1. receive error handling and break detection: if a receive error occurs, read the orer, per, and fer bits of the ssr to identify the error. after executing the necessary error handling, clear orer, per, and fer all to 0. receiving cannot resume if orer, per or fer remain set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. 2. sci status check and receive-data read: read the serial status register (ssr), check that rdrf is set to 1, then read receive data from the receive data register (rdr) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. 3. continue receiving serial data: read the rdr and rdrf bit and clear rdrf to 0 before the stop bit of the current frame is received. 218 start reception initialization read orer, per, and fer bits in ssr read reception data of rdr and clear rdrf bit in ssr to 0 end reception (3) no no yes yes read the rdrf bit in ssr rdrf = 1? per, fer, orer = 1? clear the re bit of scr to 0 yes no (2) error handling (1) all data received? figure 12.6 sample flowchart for receiving serial data 219 start of error handling orer = 1? overrun error handling fer = 1? yes break? no framing error handling per = 1? yes parity error handling clear orer, per, and fer to 0 in ssr end clear re bit in scr to 0 no no no yes yes figure 12.6 sample flowchart for receiving serial data (cont) 220 in receiving, the sci operates as follows: 1. the sci monitors the communication line. when it detects a start bit (0), the sci synchronizes internally and starts receiving. 2. receive data is shifted into the rsr in order from the lsb to the msb. 3. the parity bit and stop bit are received. after receiving these bits, the sci makes the following checks: a. parity check. the number of 1s in the receive data must match the even or odd parity setting of the o/ e bit in the smr. b. stop bit check. the stop bit value must be 1. if there are two stop bits, only the first stop bit is checked. c. status check. rdrf must be 0 so that receive data can be loaded from the rsr into the rdr. if the data passes these checks, the sci sets rdrf to 1 and stores the received data in the rdr. if one of the checks fails (receive error), the sci operates as indicated in table 12.16. note: when a receive error occurs, further receiving is disabled. while receiving, the rdrf bit is not set to 1, so be sure to clear the error flags. 4. after setting rdrf to 1, if the receive-data-full interrupt enable bit (rie) is set to 1 in the scr, the sci requests a receive-data-full interrupt (rxi). if one of the error flags (orer, per, or fer) is set to 1 and the receive-data-full interrupt enable bit (rie) in the scr is also set to 1, the sci requests a receive-error interrupt (eri). figure 12.7 shows an example of sci receive operation in the asynchronous mode. table 12.7 receive error conditions and sci operation receive error abbreviation condition data transfer overrun error orer receiving of next data ends while rdrf is still set to 1 in ssr receive data not loaded from rsr into rdr framing error fer stop bit is 0 receive data loaded from rsr into rdr parity error per parity of receive data differs from even/odd parity setting in smr receive data loaded from rsr into rdr 221 tdrf fer framing error generates eri interrupt request. 1 frame rxi interrupt handler reads data in rdr and clears rdrf to 0. 01 1 1 0/1 0 0 parity bit parity bit serial data start bit data stop bit start bit data stop bit idle (marking state) d0 d1 d7 d0 d1 d7 0/1 rxi interrupt request figure 12.7 sci receive operation (8-bit data with parity and one stop bit) 12.3.3 multiprocessor communication the multiprocessor communication function enables several processors to share a single serial communication line for sending and receiving data. the processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by a unique id. a serial communication cycle consists of an id-sending cycle that identifies the receiving processor, and a data-sending cycle. the multiprocessor bit distinguishes id-sending cycles from data-sending cycles. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. when they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their ids. the receiving processor with a matching id continues to receive further incoming data. processors with ids not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. multiple processors can send and receive data in this way. figure 12.8 shows the example of communication among processors using the multiprocessor format. 222 communication formats: four formats are available. parity-bit settings are ignored when the multiprocessor format is selected. for details see table 12.5. clock: see the description in the asynchronous mode section. receiving processor a (id = 01) (id = 02) (id = 03) (id = 04) receiving processor b receiving processor c serial communication line h'01 h'aa (mpb = 0) (mpb = 1) id-transmit cycle: receiving processor address serial data mpb: multiprocessor bit transmitting processor receiving processor d data-transmit cycle: data sent to receiving processor specified by id figure 12.8 communication among processors using multiprocessor format (sending data h'aa to receiving processor a) transmitting multiprocessor serial data: figure 12.9 shows a sample flowchart for transmitting multiprocessor serial data. the procedure is as follows (the steps correspond to the numbers in the flowchart): 1. sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr). also set mpbt (multiprocessor bit transfer) to 0 or 1 in ssr. finally, clear tdre to 0. 2. continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in tdr, then clear tdre to 0. 223 tdre = 1? write transmit data in tdr and set mpbt in ssr all data transmitted? yes tend = 1? read tend bit in ssr yes end transmission yes read tdre bit in ssr clear tdre bit to 0 no no no (1) (2) start transmission figure 12.9 sample flowchart for transmitting multiprocessor serial data in transmitting serial data, the sci operates as follows: 1. the sci monitors the tdre bit in the ssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (tdr) contains new data, and loads this data from the tdr into the transmit shift register (tsr). 2. after loading the data from the tdr into the tsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) in the scr is set to 1, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits are output, lsb first. c. multiprocessor bit: one multiprocessor bit (mpbt value) is output. d. stop bit: one or two 1 bits (stop bits) are output. e. marking: output of 1 bits continues until the start bit of the next transmit data. 224 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci loads data from the tdr into the tsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit in the ssr to 1, outputs the stop bit, then continues output of 1 bits in the marking state. if the transmit-end interrupt enable bit (teie) in the scr is set to 1, a transmit-end interrupt (tei) is requested at this time. figure 12.10 shows an example of sci receive operation in the multiprocessor format. tdre tend txi interrupt handler writes data in tdr and clears tdre to 0 txi interrupt request tei interrupt request 1 frame 01 1 1 0/1 0 1 multiprocessor bit multiprocessor bit serial data start bit data stop bit start bit data stop bit idle (marking state) d0 d1 d7 d0 d1 d7 0/1 txi interrupt request figure 12.10 sci multiprocessor transmit operation (8-bit data with multiprocessor bit and one stop bit) receiving multiprocessor serial data: figure 12.11 shows a sample flowchart for receiving multiprocessor serial data. the procedure for receiving multiprocessor serial data is listed below. 1. id receive cycle: set the mpie bit in the serial control register (scr) to 1. 2. sci status check and compare to id reception: read the serial status register (ssr), check that rdrf is set to 1, then read data from the receive data register (rdr) and compare with the processor? own id. if the id does not match the receive data, set mpie to 1 again and clear rdrf to 0. if the id matches the receive data, clear rdrf to 0. 3. receive error handling and break detection: if a receive error occurs, read the orer and fer bits in ssr to identify the error. after executing the necessary error processing, clear both orer and fer to 0. receiving cannot resume if orer or fer remain set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. 4. sci status check and data receiving: read ssr, check that rdrf is set to 1, then read data from the receive data register (rdr). 225 rdrf = 1? fer = 1? or orer =1? rdrf = 1? all data received? no end reception yes set mpie bit in scr to 1 read rdrf bit of ssr initialization clear re bit in scr to 0 yes no (1) (2) read orer and fer bits of ssr fer = 1? or orer =1? read rdrf bit in ssr read receive data from rdr is id the station? id no read orer and fer bits in ssr read receive data from rdr no error processing no yes (4) (3) yes yes no yes start reception figure 12.11 sample flowchart for receiving multiprocessor serial data 226 orer = 1? break? yes framing error handling yes start error handling overrun error handling yes fer = 1? clear orer and fer bits in ssr to 0 end no no no clear re bit in scr to 0 figure 12.11 sample flowchart for receiving multiprocessor serial data (cont) 227 figures 12.12 show examples of sci receive operation using a multiprocessor format. rdrf mpie rdr value id1 rxi interrupt request (multiprocessor interrupt), mpie = 0 rxi interrupt handler reads data in rdr and clears rdrf to 0 not station? id, so mpie is set to 1 again no rxi interrupt, rdr maintains state 01 1 1 10 1 serial data start bit stop bit (a) id does not match ( b ) id matches start bit stop bit idling (marking) d0 d1 d7 d0 d1 d7 0 mpb mpb mpb data (id1) data (data 1) rdrf mpie rdr value id1 id2 01 1 1 10 1 mpb mpb serial data start bit data (id2) data (data 2) stop bit start bit stop bit idling (marking) d0 d1 d7 d0 d1 d7 0 rxi interrupt request (multiprocessor interrupt), mpie = 0 rxi interrupt handler reads data in rdr and clears rdrf to 0 station? id, so receiving continues, with data received by the rxi interrupt processing routine mpie bit is again set to 1 mpb data2 figure 12.12 sci receive operation (8-bit data with multiprocessor bit and one stop bit) 228 12.4 interrupt the sci has four interrupt sources: transmit-end (tei), receive-error (eri), receive-data-full (rxi), and transmit-data-empty (txi). table 12.8 lists the interrupt sources and indicates their priority. these interrupts can be enabled and disabled by the tie, rie, and teie bits in the serial control register (scr). each interrupt request is sent separately to the interrupt controller. txi is requested when the tdre bit in the serial status register (ssr) is set to 1. tdre is automatically cleared to 0 when a write to the transmit data register (tdr) is performed. rxi is requested when the rdrf bit in the ssr is set to 1. eri is requested when the orer, fer, or per bit in the ssr is set to 1. tei is requested when the tend bit in the ssr is set to 1. where the txi interrupt indicates that transmit data writing is enabled, the tei interrupt indicates that the transmit operation has ended. table 12.8 sci interrupt sources interrupt source description priority eri receive error (orer, per, or fer) high rxi receive data full (rdrf) txi transmit data empty (tdre) tei transmit end (tend) low 229 12.5 notes on use the following points should be noted when using the sci. tdr write and tdre flags: the tdre bit in the serial status register (ssr) is a status flag indicating loading of transmit data from tdr into tsr. the sci sets tdre to 1 when it transfers data from tdr to tsr. data can be written to tdr regardless of the tdre bit status. if new data is written in tdr when tdre is 0, however, the old data stored in tdr will be lost because the data has not yet been transferred to the tsr. before writing transmit data to the tdr, be sure to check that tdre is set to 1. simultaneous multiple receive errors: table 12.9 indicates the state of the ssr status flags when multiple receive errors occur simultaneously. when an overrun error occurs, the rsr contents cannot be transferred to the rdr, so receive data is lost. table 12.9 ssr status flags and transfer of receive data ssr status flags receive data transfer receive error status rdrf orer fer per rsr rdr overrun error 1 1 0 0 x framing error 0 0 1 0 o parity error 0 0 0 1 o overrun error + framing error 1 1 1 0 x overrun error + parity error 1 1 0 1 x framing error + parity error 0 0 1 1 o overrun error + framing error + parity error 1111x note: o = receive data is transferred from rsr to rdr. x = receive data is not transferred from rsr to rdr. break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state, the input from the rxd pin consists of all 0s, so fer is set and the parity error flag (per) may also be set. in the break state, the sci receiver continues to operate, so if the fer bit is cleared to 0, it will be set to 1 again. receive data sampling timing and receive margin: the sci operates on a base clock of 16 times the bit rate frequency. in receiving, the sci synchronizes internally with the falling edge of the start bit, which it samples on the base clock. receive data is latched on the rising edge of the eighth base clock pulse (figure 12.13). 230 078150781505 base clock receive data (rxd) synchronization sampling timing data sampling timing 8 clocks 16 clocks start bit ?.5 clocks +7.5 clocks d0 d1 figure 12.13 receive data sampling timing the receive margin in the asynchronous mode can therefore be expressed as: m = (0.5 ? 1 2n d ?0.5 n ) ?(l ?0.5) f (1 + f) 100% m : receive margin (%) n : ratio of clock frequency to bit rate (n = 16) d : clock duty cycle (d = 0?.0) l : frame length (l = 9?2) f : absolute deviation of clock frequency from the equation above, if f = 0 and d = 0.5 the receive margin is 46.875%: d = 0.5, f = 0 m = (0.5 ?1/(2 16)) 100% = 46.875% this is a theoretical value. a reasonable margin to allow in system designs is 20?0%. 231 section 13 a/d converter (a/d) 13.1 overview the a/d converter has 10-bit resolution, and can select from a maximum of seven channels of analog inputs. 13.1.1 features the a/d converter has the following features: ? 10-bit resolution ? seven input channels ? high-speed conversion ? minimum conversion time: 6.7 m s per channel (for 20-mhz operation) ? two operating modes: single mode or scan mode ? single mode: a/d conversion on one channel ? scan mode: continuous a/d conversion on one to four channels ? four 16-bit data registers conversion results transferred to and stored in data registers corresponding to each channel. ? sample and hold function ? a/d conversion end interrupt generation an a/d conversion end interrupt (adi) request can be generated on completion of a/d conversion. ? a/d conversion can be started by mtu trigger input. 232 13.1.2 block diagram figure 13.1 is the block diagram of the a/d converter. control circuit a/d converter comparator sample and hold circuit adcr: addcsr: addra: addrb: addrc: addrd: a/d control register a/d control/status register a/d data register a a/d data register b a/d data register c a/d data register d 10-bit d/a module data bus internal data bus addra addrb addrc addrd + avcc avss an0 an1 an2 an3 an4 an5 an6 adi interrupt signal mtu trigger f /8 f /16 bus interface analog multiplexer adcsr adcr successive approximations register figure 13.1 a/d converter block diagram 233 13.1.3 pin configuration table 13.1 shows the input pins used by the a/d converter. the seven analog input pins are divided into two groups: group 0, comprising analog input pins 0 3 (an0?n3), and group 1, comprising analog input pins 4? (an4?n6). the av cc and av ss pins are for the a/d converter internal analog section power supply. table 13.1 pin configuration pin abbreviation i/o function analog supply av cc i analog section power supply analog ground av ss i analog section ground and a/d conversion reference voltage analog input 0 an0 i analog input group 0 analog input 1 an1 i analog input 2 an2 i analog input 3 an3 i analog input 4 an4 i analog input group 1 analog input 5 an5 i analog input 6 an6 i 234 13.1.4 register configuration table 13.2 shows the configuration of the a/d converter registers. table 13.2 register configuration name abbreviation r/w initial value address access size a/d data register ah addrah r h?0 h'ffff8420 8,16 a/d data register al addral r h?0 h'ffff8421 16 a/d data register bh addrbh r h?0 h'ffff8422 8,16 a/d data register bl addrbl r h?0 h'ffff8423 16 a/d data register ch addrch r h?0 h'ffff8424 8,16 a/d data register cl addrcl r h?0 h'ffff8425 16 a/d data register dh addrdh r h?0 h'ffff8426 8,16 a/d data register dl addrdl r h?0 h'ffff8427 16 a/d control/status register adcsr r/(w)* h'00 h'ffff8428 8,16 a/d control register adcr r/w h'7f h'ffff8429 8,16 note: only 0 can be written to bit 7 to clear the flag. 13.2 register descriptions 13.2.1 a/d data registers a? (addra?ddrd) the a/d data registers (addr) are 16-bit read-only registers for storing a/d conversion results. there are four of these registers, addra through addrd. the a/d-converted data is 10-bit data which is transferred to the addr for the selected channel for storage. the upper 8 bits of the converted data correspond to the upper byte of the addr, and the lower 2 bits correspond to the lower byte. bits 5? of the lower byte of the addr are reserved, and always read 0. table 13.3 shows the correspondence between the analog input channels and the addr registers. the addr registers can be read by the cpu at all times. the upper byte is read directly, but the lower byte data is transferred via a temporary register (temp). for details, see section 13.3, cpu interface. the addr registers are initialized to h'0000 by a power-on reset. 235 bit: 15 14 13 12 11 10 9 8 addrn: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 addrn: ad1 ad0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r (n = a?) table 13.3 correspondence between analog input channels and addra-addrd analog input channel group 0 group 1 a/d data register an0 an4 addra an1 an5 addrb an2 an6 addrc an3 addrd 13.2.2 a/d control/status register (adcsr) the adcsr is an 8-bit read/write register used for a/d conversion operation control and to indicate status. the adcsr is initialized to h'00 by power-on reset. bit: 7 6 5 4 3 2 1 0 adf adie adst scan cks ch2 ch1 ch0 initial value: 0 0 0 0 0 0 0 0 r/w: r/(w)* r/w r/w r/w r/w r/w r/w r/w note: the only value that can be written is a 0 to clear the flag. 236 ? bit 7?/d end flag (adf): this status flag indicates that a/d conversion has ended. bit 7: adf description 0 clear conditions (initial value) with adf = 1, by reading the adf flag then writing 0 in adf 1 set conditions ? single mode: when a/d conversion ends after conversion for all designated channels ? scan mode: after one round of a/d conversion for all specified channels ? bit 6?/d interrupt enable (adie): enables or disables interrupt requests (adi) after a/d conversion ends. bit 6: adie description 0 disables interrupt requests (adi) after a/d conversion ends (initial value) 1 enables interrupt requests (adi) after a/d conversion ends ? bit 5?/d start (adst): selects start or stop for a/d conversion. the adst bit remains set to 1 during a/d conversion. it can also be set to 1 by mtu trigger input. bit 5: adst description 0 a/d conversion halted (initial value) 1 single mode: start a/d conversion. automatically cleared to 0 after conversion for the designated channel ends. scan mode: start a/d conversion. continuous conversion until 0 cleared by software, and by power-on reset. ? bit 4?can mode (scan): selects single mode or scan mode for a/d conversion. for details of the operation in single mode and scan mode, see section 13.4, operation. change the mode only when adst = 0. bit 4: scan description 0 single mode (initial value) 1 scan mode 237 ? bit 3?lock select (cks): sets the a/d conversion time. change the conversion time only when adst = 0. bit 3: cks description 0 conversion time = 266 states (max.) (initial value) 1 conversion time = 134 states (max.) ? bits 2??hannel select 2? (ch2?h0): these bits, along with the scan bit, select the analog input channel. change the channel selection only when adst = 0. description bit 2: ch2 bit 1: ch1 bit 0: ch0 single mode scan mode 0 0 0 an0 (initial value) an0 (initial value) 0 0 1 an1 an0?n1 0 1 0 an2 an0?n2 0 1 1 an3 an0?n3 1 0 0 an4 an4 1 0 1 an5 an4, an5 1 1 0 an6 an4?n6 1 1 1 reserved* reserved* note: this setting is reserved and must not be used. 13.2.3 a/d control register (adcr) the a/d control register (adcr) is an 8-bit read/write register that enables or disables starting of a/d conversion by mtu trigger input. the adcr is initialized to h'7f by a power-on reset or in standby mode. bit: 7 6 5 4 3 2 1 0 trge initial value: 0 1 1 1 1 1 1 1 r/w: r/w r r r r r r r 238 ? bit 7?rigger enable (trge): enables or disables starting of a/d conversion by mtu trigger input. bit 7: trge description 0 disables a/d conversion start by mtu trigger input (initial value) 1 a/d conversion is started by mtu trigger ? bits 6??eserved: these bits always read 1. the write value should always be 1. 13.3 cpu interface addra?ddrd are 16-bit registers, but they are connected to the cpu by an 8-bit data bus. therefore, while the upper byte is accessed directly by the cpu, the lower byte is accessed via an 8-bit temporary register (temp). data is read from an addr register as follows. when the upper byte is read, the upper-byte value is transferred directly to the cpu and the lower-byte value is transferred into temp. next, when the lower byte is read, the temp contents are transferred to the cpu. when reading an addr register, always read the upper byte before the lower byte. this operation can be performed by reading addr from the upper byte address using a word transfer instruction (such as mov.w). it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 13.2 shows the data flow for access to an addr register. 239 upper-byte read cpu (h'aa) bus interface module data bus addrnh (h'aa) addrnl (h'40) temp (h'40) lower-byte read cpu (h'40) bus interface module data bus addrnh (h'aa) addrnl (h'40) (n = a?) (n = a?) temp (h'40) figure 13.2 addr access operation (reading h'aa40) 240 13.4 operation the a/d converter operates by successive approximations with 10-bit resolution. it has two operating modes: single mode and scan mode.. the operation in these two modes is described below. 13.4.1 single mode (scan = 0) single mode should be selected for a/d conversion on only one channel. a/d conversion starts when the adst bit in the a/d control/status register (adcsr) is set to 1 by software or mtu trigger input. the adst bit remains set to 1 during a/d conversion, and is automatically cleared to 0 when conversion ends. when conversion ends, the adf bit in adcsr is set to 1. if the adie bit in adcsr is also 1, an adi interrupt is requested. to clear the adf bit, first read adf when set to 1, then write 0 in adf. to prevent incorrect operation, a/d conversion should be halted by clearing the adst bit to 0 before changing the mode or analog input channel. after the change is made, a/d conversion is restarted by setting the adst bit to 1 (the mode or channel change and setting of the adst bit can be carried out simultaneously). an example of the operation when analog input channel 1 (an1) is selected and a/d conversion is performed in single mode is described below. figure 13.3 shows a timing diagram for this example. 1. single mode is selected (scan = 0), input channel an1 is selected (ch2 = ch1 = 0, ch0 = 1), the a/d interrupt request is enabled (adie = 1), and a/d conversion is started (adst = 1). 2. when a/d conversion is completed, the result is transferred to addrb. at the same time adf is set to 1, adst is cleared to 0, and the a/d converter becomes idle. 3. since adf = 1 and adie = 1, an adi interrupt is requested. 4. the a/d interrupt service routine is started. 5. the routine reads adf set to 1, then writes 0 in adf. 6. the routine reads and processes the conversion result (addrb). 7. execution of the a/d interrupt service routine ends. after this, if the adst bit is set to 1, a/d conversion starts again and steps 2 to 7 are repeated. 241 adie adst adf channel 0 (an0) channel 1 (an1) channel 2 (an2) channel 3 (an3) addra addrb addrc addrd a/d conversion starts conversion standby conversion standby conversion standby conversion result read conversion result read conversion standby a/d conversion 1 a/d conversion 2 a/d conversion result 1 a/d conversion result 2 conversion standby conversion standby set* set* set* clear* clear* note: vertical arrows ( ) indicate instructions executed by software. figure 13.3 example of a/d converter operation (single mode, channel 1 selected) 242 13.4.2 scan mode (scan = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit in the a/d control/status register (adcsr) is set to 1 by software or mtu trigger input, a/d conversion starts on the first channel in the group (an0 when ch2 = 0; an4 when ch1 = 1). when more than one channel has been selected, a/d conversion starts on the second channel (an1 or an5) as soon as conversion ends on the first channel. a/d conversion is performed repeatedly on all the selected channels until the adst bit is cleared to 0. the conversion results are transferred to and stored in the addr register for each channel. to prevent incorrect operation, a/d conversion should be halted by clearing the adst bit to 0 before changing the mode or analog input channels. after the change is made, the first channel is selected and a/d conversion is restarted by setting the adst bit to 1 (the mode or channel change and setting of the adst bit can be carried out simultaneously). an example of the a/d conversion operation in scan mode when three channels (an0?n2) in group 0 are selected is described below. figure 13.4 shows a timing diagram for this example. 1. scan mode is selected (scan = 1), group 0 is selected as the scan group (ch2 = 0), analog input channels an0-an2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. a/d conversion starts on the first channel (an0), and when completed, the result is transferred to addra. next, conversion of the second channel (an1) starts automatically. 3. conversion proceeds in the same way through the third channel (an2). 4. when conversion is completed for all the selected channels (an0?n2), adf is set to 1, the first channel (an0) is selected again, and conversion is performed on that channel. if the adie bit is also 1, an adi interrupt is requested when conversion is completed. 5. steps 2 to 4 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after this, if the adst bit is set to 1, a/d conversion starts again from the first channel (an0). 243 adst adf conversion standby conversion standby conversion standby a/d conversion 1 conversion standby conversion standby a/d conversion result 4 a/d conversion result 2 a/d conversion result 3 transfer channel 0 (an0) channel 1 (an1) channel 2 (an2) channel 3 (an3) addra addrb addrc addrd set * 1 clear * 1 clear * 1 a/d conversion 2 a/d conversion 5 * 2 conversion standby conversion standby a/d conversion 3 continuous a/d conversion notes: 1. vertical arrows ( ) indicate instructions executed by software. 2. data currently being converted is ignored. conversion standby a/d conversion 4 a/d conversion result 1 figure 13.4 example of a/d converter operation (scan mode, channels an0?n2 selected) 244 13.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample and hold circuit. the a/d converter samples the analog input at time t d after the adst bit is set to 1 in the a/d control/status register (adcsr), then starts conversion. figure 13.5 shows the a/d conversion timing, and table 13.4 shows a/d conversion times. as shown in figure 13.5, a/d conversion time tconv consists of a/d conversion start delay time t d and analog input sampling time t spl . the length of td is not fixed, but is determined by the timing of the write to adscr. the total conversion time therefore varies within the ranges shown in table 13.4. in scan mode, the t conv values given in table 13.4 apply to the first conversion. in the second and subsequent conversions, t conv is fixed at 256 states when cks = 0 or 128 states when cks = 1. 245 (1) (2) ck adf address write signal input sampling timing t d t spl t conv (1): (2): t d : t spl : t conv : adcsr write cycle adcsr address a/d conversion start delay time input sampling time a/d conversion time figure 13.5 a/d conversion timing table 13.4 a/d conversion times (single mode) cks = 0 cks = 1 symbol min typ max min typ max a/d conversion start delay time t d 10?7 6 ? input sampling time t spl ?4 ?2 a/d conversion time t ccnv 259 266 131 134 note: unit: states (t cyc ) 246 13.4.4 mtu trigger input timing a/d conversion can also be started by mtu trigger input. when the trge bit is set to 1 in the a/d control register (adcr), input from the mtu functions as trigger input. when an mtu trigger is detected, the adst bit is set to 1 in the a/d control/status register (adst), and the a/d converter is started. other operations, for both single mode and scan mode, are the same as when the adst bit is set to 1 by software, . figure 13.6 shows the timing for mtu trigger input. a/d conversion ck mtu trigger signal adst figure 13.6 external trigger input timing 13.5 a/d conversion precision definitions the a/d converter converts analog values input from analog input channels to 10-bit digital values by comparing them with an analog reference voltage. in this operation, the absolute precision of the a/d conversion (i.e. the deviation between the input analog value and the output digital value) includes the following kinds of error. 1. offset error 2. full-scale error 3. quantization error 4. nonlinearity error 247 the above four kinds of error are described below with reference to figure 13.7. for the sake of clarity, this figure shows 3-bit a/d conversion rather than 10-bit a/d conversion. offset error (see figure 13.7 (1)) is the deviation between the actual a/d conversion characteristic and the ideal a/d conversion characteristic when the digital output value changes from the minimum value (zero voltage) of 0000000000 (000 in the figure) to 0000000001 (001 in the figure ). full-scale error (see figure 13.7 (2)) is the deviation between the actual a/d conversion characteristic and the ideal a/d conversion characteristic when the digital output value changes from 1111111110 (110 in the figure) to the maximum value (full-scale voltage) of 111111111 (111 in the figure). quantization error is the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 13.7 (3)). nonlinearity error is the deviation between the actual a/d conversion characteristic and the ideal a/d conversion characteristic from zero voltage to full-scale voltage (see figure 13.7 (4)). this does not include offset error, full-scale error, and quantization error. 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 fs 111 110 101 100 011 010 001 000 analog input voltage (3) quantization error (4) nonlinearity error (2) full-scale error ideal a/d conversion characteristic digital output fs: full-scale voltage fs actual a/d conversion characteristic (1) offset error ideal a/d conversion characteristic digital output analog input voltage figure 13.7 a/d conversion precision definitions 248 13.6 notes on use the following points should be noted when using the a/d converter. 13.6.1 analog voltage settings analog input voltage range: the voltage applied to analog input pins during a/d conversion should be in the range av ss ann av cc (n = 0 to 6). av cc and av ss input voltages: for the av cc and av ss input voltages, set av cc = 3.3 v 10%, and av ss = v ss . when the a/d converter is not used, set av cc = v cc and av ss = v ss . 13.6.2 handling of analog input pins to prevent damage from surges and other abnormal voltages at the analog input pins (an0?n6), connect a protection circuit such as that shown in figure 13.8. this circuit also includes a cr filter function that suppresses error due to noise. the circuit shown here is only a design example; circuit constants must be decided on the basis of the actual operating conditions. figure 13.9 shows an equivalent circuit for the analog input pins, and table 13.5 summarizes the analog input pin specifications. SH7011 avcc an0?n6 avss 100 w * note: 0.1 m f 10 m f 0.01 m f figure 13.8 example of analog input pin protection circuit 249 an0?n6 1.0 k w 20 pf 1 m w analog multiplexer a/d converter note: values are reference values. figure 13.9 analog input pin equivalent circuit table 13.5 analog input pin specifications item min max unit analog input capacitance 20 pf permitted signal source impedance 3 k w 251 section 14 pin function controller 14.1 overview the pin function controller (pfc) is composed of registers for selecting the function of multiplexed pins and the direction of input/output. table 14.1 lists the SH7011? multiplexed pins. these multiplexed pins are initially set as input ports after a power-on reset. table 14.1 multiplexed pins port function 1 (related module) function 2 (related module) pin e pe7 i/o (port) tioc2b i/o (mtu) 98 e pe6 i/o (port) tioc2a i/o (mtu) 83 e pe5 i/o (port) tioc1b i/o (mtu) 82 e pe4 i/o (port) tioc1a i/o (mtu) 81 e pe2 i/o (port) tioc0c i/o (mtu) 79 e pe0 i/o (port) tioc0a i/o (mtu) 78 14.2 register configuration table 14.2 summarizes the registers of the pin function controller. table 14.2 register configuration name abbreviation r/w initial value address access size port a i/o register h paiorh r/w h'0000 h'ffff8384 h'ffff8385 8, 16 port e i/o register peior r/w h'0000 h'ffff83b4 h'ffff83b5 8, 16 port e control register 2 pecr2 r/w h'0000 h'ffff83ba h'ffff83bb 8, 16 252 14.3 register descriptions 14.3.1 port a i/o register h (paiorh) port a i/o register h (paiorh) is a 16-bit read/write register that selects input or output for pins pa19 and pa18 in port a. a pin in port a is an output pin if its corresponding paiorh bit is set to 1, and an input pin if the bit is cleared to 0. paiorh is initialized to h'0000 by a power-on reset; however, it is not initialized in sleep mode, so the previous data is maintained. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 pa19 ior pa18 ior initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r/w r/w r r 14.3.2 port e i/o register (peior) the port e i/o register (peior) is a 16-bit read/write register that selects input or output for nine pins in port e. bits pe17ior?e4ior, pe2ior, and pe0ior correspond to multiplexed pins. when the port e pin functions are pex, a pin in port e is an output pin if its corresponding peior bit is set to 1, and an input pin if the bit is cleared to 0. peior is initialized to h'0000 by a power-on reset; however, it is not initialized in sleep mode, so the previous data is maintained. bit: 15 14 13 12 11 10 9 8 pe14 ior pe13 ior pe12 ior initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r r r r 253 bit: 7 6 5 4 3 2 1 0 pe7 ior pe6 ior pe5 ior pe4 ior pe2 ior pe0 ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r/w r r/w 14.3.3 port e control register 2 (pecr2) port e control register 2 (pecr2) is a 16-bit read/write register that selects the functions of the six multiplexed pins in port e. pecr2 is initialized to h'0000 by a power-on reset; however, it is not initialized in sleep mode, so the previous data is maintained. bit: 15 14 13 12 11 10 9 8 pe7md pe6md pe5md pe4md initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r r/w r r/w r r/w bit: 7 6 5 4 3 2 1 0 pe2 md0 pe0 md0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r/w r r r r/w ? bit 15?eserved: this bit always reads as 0. the write value should always be 0. ? bit 14?e7 mode (pe7md): selects the function of the pe7/tioc2b pin. bit 14: pe7md description 0 general input/output (pe7) (initial value) 1 mtu input capture input/output compare output (tioc2b) ? bit 13 ?eserved: this bit always reads as 0. the write value should always be 0. 254 ? bit 12?e6 mode (pe6md): selects the function of the pe6/tioc2a pin. bit 12: pe6md description 0 general input/output (pe6) (initial value) 1 mtu input capture input/output compare output (tioc2a) ? bit 11?eserved: this bit always reads as 0. the write value should always be 0. ? bit 10?e5 mode (pe5md): selects the function of the pe5/tioc1b pin. bit 10: pe5md description 0 general input/output (pe5) (initial value) 1 mtu input capture input/output compare output (tioc1b) ? bit 9?eserved: this bit always reads as 0. the write value should always be 0. ? bit 8?e4 mode (pe4md): selects the function of the pe4/tioc1a pin. bit 8: pe4md description 0 general input/output (pe4) (initial value) 1 mtu input capture input/output compare output (tioc1a) ? bits 7??eserved. these bits always read 0. the write value should always be 0. ? bit 4?e2 mode 0 (pe2md0): selects the function of the pe2/tioc0c pin. bit 4: pe2md0 description 0 general input/output (pe2) (initial value) 1 mtu input capture input/output compare output (tioc0c) ? bits 3??eserved. these bits always read 0. the write value should always be 0. ? bit 0?e0 mode 0 (pe0md0): selects the function of the pe0/tioc0a pin. bit 0: pe0md0 description 0 general input/output (pe0) (initial value) 1 mtu input capture input/output compare output (tioc0a) 255 section 15 i/o ports (i/o) 15.1 overview there are two ports, a and e. the pin function controller (pfc) is used to select the function of multiplexed pins. the ports each have one data register for storing pin data. all pins are initially set as input port pins after a power-on reset. 15.2 port a port a is a 2-pin input/output port, as shown in figure 15.1. pa19 (input/output) pa18 (input/output) port a figure 15.1 port a 15.2.1 register configuration table 15.1 summarizes the port a register. table 15.1 port a register name abbreviation r/w initial value address access size port a data register h padrh r/w h'0000 h'ffff8380 h'ffff8381 8, 16 256 15.2.2 port a data register h (padrh) padrh is a 16-bit read/write register that stores data for port a. the bits pa19dr?a18dr correspond to the pa19 pin and pa18 pin. when the pins are used as ordinary outputs, they will output whatever value is written in the padrh; when padrh is read, the register value will be output regardless of the pin status. when the pins are used as ordinary inputs, the pin status rather than the register value is read directly when padrh is read. when a value is written to padrh, that value can be written into padrh, but it will not affect the pin status. table 15.2 shows the read/write operations of the port a data register. padrh is initialized by an external power-on reset. however, padrh is not initialized in sleep mode, so the previous data is maintained. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 pa19dr pa18dr initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r/w r/w r r table 15.2 port a data register (padr) read/write operations paior pin function read write 0 input pin status can write to padr, but it has no effect on pin status 1 output padr value value written is output by pin 257 15.3 port e port e is a 9-pin input/output port, as shown in table 15.2. pe12 (i/o) pe7 (i/o)/tioc2b (i/o) pe14 (i/o) pe13 (i/o) pe4 (i/o)/tioc1a (i/o) pe2 (i/o)/tioc0c (i/o) pe0 (i/o)/tioc0a (i/o) pe6 (i/o)/tioc2a (i/o) pe5 (i/o)/tioc1b (i/o) port e figure 15.2 port e 15.3.1 register configuration table 15.3 summarizes the port e register. table 15.3 port e register name abbreviation r/w initial value address access size port e data register pedr r/w h'0000 h'ffff83b0 h'ffff83b1 8, 16 258 15.3.2 port e data register (pedr) pedr is a 16-bit read/write register that stores data for port e. table 15.5 shows the correspondence between pedr bits and port e pins. when the pins are used as ordinary outputs, they will output whatever value is written in the pedr; when pedr is read, the register value will be read regardless of the pin status. when the pins are used as ordinary inputs, the pin status rather than the register value is read directly when pedr is read. when a value is written to pedr, that value can be written into pedr, but it will not affect the pin status. table 15.4 shows the read/write operations of the port e data register. pedr is initialized by a power-on reset. however, pedr is not initialized for a sleep mode, so the previous data is retained. bit: 15 14 13 12 11 10 9 8 pe14dr pe13dr pe12dr initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r r r r bit: 7 6 5 4 3 2 1 0 pe7dr pe6dr pe5dr pe4dr pe2dr pe0dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r/w r r/w table 15.4 read/write operation of the port e data register (pedr) peior pin status read write 0 ordinary input pin status can write to pedr, but it has no effect on pin status other function pin status can write to pedr, but it has no effect on pin status 1 ordinary output pedr value value written is output by pin other function pedr value can write to pedr, but it has no effect on pin status 259 table 15.5 correspondence between port e data register (pedr) bits and port e pins pedr bit port e pin pe14dr pe14 pe13dr pe13 pe12dr pe12 pe7dr pe7/tioc2b pe6dr pe6/tioc2a pe5dr pe5/tioc1b pe4dr pe4/tioc1a pe2dr pe2/tioc0c pe0dr pe0/tioc0a 261 section 16 ram 16.1 overview the SH7011 has 4 kbytes of on-chip ram. the on-chip ram is connected to the cpu by a 32-bit data bus (figure 16.1). the cpu can access data in the on-chip ram in 8, 16, or 32 bit widths. on-chip ram data can always be accessed in one state, making the ram ideal for use as a program area, stack area, or data area, which require high-speed access. the contents of the on- chip ram are held in sleep mode. memory area addresses h'ffffe000 to h'ffffffff are allocated to the on-chip ram. h'fffff000 h'fffff004 h'fffff001 h'fffff005 h'fffff002 h'fffff006 h'fffff003 h'fffff007 h'fffffffc h'fffffffd h'fffffffe h'ffffffff on-chip ram internal data bus (32 bits) figure 16.1 block diagram of ram 263 section 17 electrical characteristics 17.1 absolute maximum ratings table 17.1 absolute maximum ratings item symbol rating unit power supply voltage v cc ?.3 to +7.0 v input voltage (other than a/d ports) v in ?.3 to v cc + 0.3 v input voltage (a/d ports) v in ?.3 to av cc + 0.3 v analog supply voltage av cc ?.3 to +7.0 v analog input voltage v an ?.3 to av cc + 0.3 v operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c note: operating the lsi in excess of the absolute maximum ratings may result in permanent damage. 264 17.2 dc characteristics table 17.2 dc characteristics (conditions: v cc = 3.0 to 3.6v, av cc = 3.0 to 5.5v, av cc 3 v cc , v ss = av ss = 0v, t a = ?0 to +75 c) item pin symbol min typ max unit measurement conditions input high- level voltage res , nmi, pe0, pe2, pe4 to pe7, pe12 to pe14 v ih v cc ?0.7 v cc + 0.3 v extal v cc 0.7 v cc + 0.3 v a/d port 2.2 av cc + 0.3 v other input pins 2.2 v cc + 0.3 v input low- level voltage res , nmi, pe0, pe2, pe4 to pe7, pe12 to pe14 v il ?.3 v cc 0.1 v other input pins ?.3 v cc 0.2 v schmitt trigger input voltage pe0, pe2, pe4 to pe7, pe12 to pe14 v t + v t v t + v t v cc 0.9 v cc 0.07 v cc 0.2 v v v input leak current res , nmi, pe0, pe2, pe4 to pe7, pe12 to pe14 | l in | 1.0 m av in = 0.5 to v cc ?0.5v a/d port 1.0 m av in = 0.5 to av cc ?0.5v other input pins 1.0 m av in = 0.5 to v cc ?0.5v three?tate leak current (while off) a21?1, d15?0, cs3 cs0 , wrx , rd , port a, e | i tsi | 1.0 m av in = 0.5 to v cc ?0.5v 265 table 17.2 dc characteristics (conditions: v cc = 3.0 to 3.6v, av cc = 3.0 to 5.5v, av cc 3 v cc , v ss = av ss = 0v, t a = ?0 to +75 c) (cont) item pin symbol min typ max unit measurement conditions output all output pins v oh v cc ?0.5 vi oh = ?00 m a high-level voltage v cc ?1.0 v i oh = ?ma output low- level voltage all output pins v ol 0.4 v i ol = 1.6ma input res c in 80 pf vin= 0v capaci- nmi 50 pf f = 1 mhz tance all other input pins 20 pf ta = 25 c current consump- during normal operations i cc 80 130 ma f = 20mhz tion during sleep mode 70 110 ma f = 20mhz analog supply current ai cc ?8 ma f = 20mhz notes: 1. do not release av cc and av ss pins when not using the a/d converter. connect av cc pin to v cc and av ss pin to v ss . 2. the value for consumed current is with conditions of v ih min = v cc ?0.5v and v il max = 0.5v, with no burden on any of the output pins. 266 table 17.3 permitted output current values (conditions: v cc = 3.0 to 3.6v, av cc = 3.0 to 5.5v, av cc 3 v cc , v ss = av ss = 0v, t a = ?0 to +75 c) item symbol min typ max unit output low-level permissible current (per pin) i ol 2.0 ma output low-level permissible current (total) ? i ol 80ma output high-level permissible current (per pin) ? oh 2.0 ma output high-level permissible current (total) ? (? oh )25ma note: to assure lsi reliability, do not exceed the output values listed in this table. 17.3 ac characteristics 17.3.1 clock timing table 17.4 clock timing (conditions: v cc = 3.0 to 3.6v, av cc = 3.0 to 5.5v, av cc 3 v cc , v ss = av ss = 0v, t a = ?0 to +75 c) item symbol min max unit figures operating frequency f op 4 20 mhz 17.1 clock cycle time t cyc 50 250 ns clock low-level pulse width t cl 10 ns clock high-level pulse width t ch 10 ns clock rise time t cr ?0ns clock fall time t cf ?0ns extal clock input frequency f ex 4 20 mhz 17.2 extal clock input cycle time t excyc 50 250 ns extal clock low-level input pulse width t exl 10 ns extal clock high-level input pulse width t exh 10 ns extal clock input rise time t exr ? ns extal clock input fall time t exf ? ns reset oscillation settling time t osc1 20 ms 17.3 267 t cyc t cl t ch 1/2v cc 1/2v cc t cf t cr ck figure 17.1 system clock timing t excyc t exl t exh v ih v ih 1/2v cc v il v il 1/2v cc t exf t exr extal v ih figure 17.2 extal clock input timing t osc1 v cc min ck v cc res figure 17.3 oscillation settling time 268 17.3.2 control signal timing table 17.5 control signal timing (conditions: v cc = 3.0 to 3.6v, av cc = 3.0 to 5.5v, av cc 3 v cc , v ss = av ss = 0v, t a = ?0 to +75 c) item symbol min max unit figure res rise/fall t resr , t resf 200 ns 17.4 res pulse width t resw 40 t cyc nmi rise/fall t nmir , t nmif 200 ns 17.5 res setup time * t ress 100 ns 17.4 nmi setup time (during edge detection) t nmis 100 ns 17.5 irq7 irq0 setup time (edge detection) t irqes 100 ns irq7 irq0 setup time (level detection) t irqls 100 ns nmi hold time t nmih 50 ns 17.5 irq7 irq0 hold time t irqeh 50 ns note: the res , nmi, and irq7 e irq0 signals are asynchronous inputs, but when the setup times shown here are provided, the signals are considered to have produced changes at clock rise (for res ) or clock fall (for nmi and irq7 e irq0 ). if the setup times are not provided, recognition is delayed until the next clock rise or fall. 269 ck res t resf t resw t resr t ress t ress v ih v ih v il v il figure 17.4 reset input timing t nmih t nmis t nmir, t nmif v ih v il t irqeh t irqes v ih v il t irqls ck nmi irq edge irq level figure 17.5 interrupt signal input timing 270 17.3.3 bus timing table 17.6 bus timing (conditions: v cc = 3.0 to 3.6v, av cc = 3.0 to 5.5v, av cc 3 v cc , v ss = av ss = 0v, t a = ?0 to +75 c) item symbol min max unit figure address delay time t ad 3* 3 40 ns 17.6, 7 cs delay time 1 t csd1 3* 3 40 ns cs delay time 2 t csd2 3* 3 40 ns read strobe delay time 1 t rsd1 3* 3 40 ns read strobe delay time 2 t rsd2 3* 3 40 ns read data setup time t rds * 4 45 ns read data hold time t rdh 0 ns write strobe delay time 1 t wsd1 3* 3 40 ns write strobe delay time 2 t wsd2 3* 3 40 ns write data delay time t wdd ?0ns write data hold time t wdh 0 30* 2 ns wait setup time t wts 20 ns 17.8 wait hold time t wth 0 ns read data access time t acc * 1 * 5 t cyc (n+2) ?75 ns 17.6, 7 access time from read strobe t ce * 1 t cyc (n+1.5) ?75 ns write address setup time with respect to wr fall t as 0 ns write address hold time with respect to wr fall t wr 5 ns write data hold time with respect to wr fall t wrh 0 ns notes: n is the wait number. 1. if the access time is satisfied, then the t rds need not be satisfied. 2. t wdh (max) is a reference value. 3. the delay time min values are reference values (typ). 4. t rds is a reference value. 5. depending on the operating frequency of the chip, there may be no memory that can be connected in no-wait mode. in this case, a wait should be inserted. 271 t1 t2 ck a21?1 t wdh t wdd t wsd1 t wsd2 t acc t rds t rdh t rsd1 t oe t rsd2 t csd2 t csd1 t ad t as t wr t wrh csn note: t rdh is specified from fastest negate timing of a21ea0, csn and rd . (during read) (during read) rd d15ed0 d15ed0 wr (during write) (during write) figure 17.6 basic cycle (no waits) 272 ck a21?1 t1 tw t2 t ad t csd1 t rsd1 t wsd1 t wdd t rsd2 t csd2 t rds t rdh t wsd2 t wdh t oe t acc t as t wrh t wr note : t rdh is specified from fastest negate timing of a21?0, csn and rd . csn rd d15ed0 d15ed0 (during read) (during read) (during write) (during write) wrx figure 17.7 basic cycle (software waits) 273 ck a21?1 t1 tw two tw t2 t wts t wth t wts t wth csn rd wrx wait (during read) (during read) (during write) (during write) d15ed0 d15ed0 figure 17.8 basic cycle (2 software waits + wait due to wait signal) 274 17.3.4 multifunction timer pulse unit timing table 17.7 multifunction timer pulse unit timing (conditions:v cc = 3.0 to 3.6v, av cc = 3.0 to 5.5v, av cc 3 v cc , v ss = av ss = 0v, t a = ?0 to +75 c) item symbol min max unit figure output compare output delay time t tocd 100 ns 17.9 input capture input setup time t tics 100 ns ck t tocd t tics input capture input output compare output figure 17.9 mtu i/o timing 275 17.3.5 i/o port timing table 17.8 i/o port timing (conditions:v cc = 3.0 to 3.6v, av cc = 3.0 to 5.5v, av cc 3 v cc , v ss = av ss = 0v, t a = ?0 to +75 c) item symbol min max unit figure port output data delay time t pwd 100 ns 17.10 port input hold time t prh 100 ns port input setup time t prs 100 ns t prs t prh t pwd t1 t2 ck port (read) port (write) figure 17.10 i/o port i/o timing 276 17.3.6 serial communication interface timing table 17.9 serial communication interface timing (conditions:v cc = 3.0 to 3.6v, av cc = 3.0 to 5.5v, av cc 3 v cc , v ss = av ss = 0v, t a = ?0 to +75 c) item symbol min max unit figure transmit data delay time (clock sync) t txd 100 ns 17.11 receive data setup time (clock sync) t rxs 100 ns receive data hold time (clock sync) t rxh 100 ns t scyc t txd t rxs t rxh internal serial clock txd (transmit data) rxd (receive data) figure 17.11 sci i/o timing (clock sync mode) 277 17.3.7 a/d converter timing table 17.10 a/d converter timing (conditions:v cc = 3.0 to 3.6v, av cc = 3.0 to 5.5v, av cc 3 v cc , v ss = av ss = 0v, t a = ?0 to +75 c) item symbol min typ max unit figure a/d conversion start delay time cks = 0 t d 10 17 t cyc 17.12 cks = 1 6 9 input sampling time cks = 0 t rxs ?4 cks = 1 32 a/d conversion time cks = 0 t rxh 259 266 cks = 1 131 134 adf t d (1) (2) t d t spl t conv t spl t conv : adcsr write cycle : adcsr address : a/d conversion start delay time : input sampling time : a/d conversion time address write signal input sampling timing (1) (2) figure 17.12 analog conversion timing 278 17.3.8 measurement conditions for ac characteristic input reference levels: ? high level: 2.2 v ? low level: 0.8 v output reference levels: ? high level: 2.0 v ? low level: 0.8 v i ol v ref c l i oh v lsi output pin dut output c l is set with the following pins, including the total capacitance of the measurement equipment etc: note: 30 pf: 50 pf: 70 pf: i ol , i oh : ck, cs0ecs3 a21ea1, d15ed0, rd, wrx port output and peripheral module output pins other than the above. see table 17.3, permitted output current values. figure 17.13 output added circuit 279 17.4 a/d converter characteristics table 17.11 a/d converter characteristics (conditions:v cc = 3.0 to 3.6v, av cc = 3.0 to 5.5v, av cc 3 v cc , v ss = av ss = 0v, t a = ?0 to +75 c, cks = 0) 20 mhz item min typ max unit resolution 10 10 10 bit conversion time 13.4 m s analog input capacity 20 pf permission signal source impedance 1 k w non-linearity error* 3 lsb offset error* 3 lsb full scale error* 3 lsb quantize error* 0.5 lsb absolute error 4 lsb note: * reference values table 17.12 a/d converter characteristics (conditions:v cc = 3.0 to 3.6v, av cc = 3.0 to 5.5v, av cc 3 v cc , v ss = av ss = 0v, t a = ?0 to +75 c, cks = 1) 20 mhz item min typ max unit resolution 10 10 10 bit conversion time 6.7 m s analog input capacity 20 pf permission signal source impedance 1 k w non-linearity error* 5 lsb offset error* 5 lsb full scale error* 5 lsb quantize error* 0.5 lsb absolute error 6 lsb note: * reference values 281 appendix a on-chip supporting module registers table a.1 on-chip supporting module registers address register bit names h'ffffxxxx abbr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module 81b0 smr chr pe o/e stop mp cks1 cks0 sci 81b1 brr 81b2 scr tie rie te re mpie teie 81b3 tdr 81b4 ssr tdre rdrf orer fer per tend mpb mpbt 81b5 rdr 8240 tstr cst2 cst1 cst0 common mtu 8241 tsyr sync2 sync1 sync0 8260 tcr0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 ch0 8261 tmdr0 bfb bfa md3 md2 md1 md0 8262 tior0h ioa3 ioa2 ioa1 ioa0 8263 tior0l ioc3 ioc2 ioc1 ioc0 8264 tier0 ttge tciev tgied tgiec tgieb tgiea 8265 tsr0 tcfv tgfd tgfc tgfb tgfa 8266 tcnt0 8267 8268 tgr0a 8269 826a tgr0b 826b 826c tgr0c 826d 826e tgr0d 826f 282 table a.1 on-chip supporting module registers (cont) address register bit names h'ffffxxxx abbr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module 8280 tcr1 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 ch1 mtu 8281 tmdr1 md3 md2 md1 md0 8282 tior1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 8284 tier1 ttge tciev tgieb tgiea 8285 tsr1 tcfv tgfb tgfa 8286 tcnt1 8287 8288 tgr1a 8289 828a tgr1b 828b 82a0 tcr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 ch2 82a1 tmdr2 md3 md2 md1 md0 82a2 tior2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 82a4 tier2 ttge tciev tgieb tgiea 82a5 tsr2 tcfv tgfb tgfa 82a6 tcnt2 82a7 82a8 tgr2a 82a9 82aa tgr2b 82ab 8348 ipra (irq0) (irq0) (irq0) (irq0) (irq1) (irq1) (irq1) (irq1) intc 8349 (irq2) (irq2) (irq2) (irq2) (irq3) (irq3) (irq3) (irq3) 834a iprb (irq4) (irq4) (irq4) (irq4) (irq5) (irq5) (irq5) (irq5) 834b (irq6) (irq6) (irq6) (irq6) (irq7) (irq7) (irq7) (irq7) 834c iprc 834d 834e iprd (mtu0) (mtu0) (mtu0) (mtu0) (mtu0) (mtu0) (mtu0) (mtu0) 834f (mtu1) (mtu1) (mtu1) (mtu1) (mtu1) (mtu1) (mtu1) (mtu1) 8350 ipre (mtu2) (mtu2) (mtu2) (mtu2) (mtu2) (mtu2) (mtu2) (mtu2) 8351 8352 iprf 8353 (sci) (sci) (sci) (sci) 283 table a.1 on-chip supporting module registers (cont) address register bit names h'ffffxxxx abbr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module 8354 iprg (a/d) (a/d) (a/d) (a/d) intc 8355 (cmt0) (cmt0) (cmt0) (cmt0) (cmt1) (cmt1) (cmt1) (cmt1) 8356 iprh (tim1,2) (tim1,2) (tim1,2) (tim1,2) 8357 8358 icr nmil nmie 8359 irq0s irq1s irq2s irq3s irq4s irq5s irq6s irq7s 835a isr 835b irq0f irq1f irq2f irq3f irq4f irq5f irq6f irq7f 8380 padrh i/o port a 8381 pa19dr pa18dr 8384 paiorh pfc 8385 pa19ior pa18ior 83b0 pedr pe14dr pe13dr pe12dr i/o port e 83b1 pe7dr pe6dr pe5dr pe4dr pe2dr pe0dr 83b4 peior pe14ior pe13ior pe12ior pfc 83b5 pe7ior pe6ior pe5ior pe4ior pe2ior pe0ior 83ba pecr2 pe7md pe6md pe5md pe4md 83bb pe2md0 pe0md0 83d0 cmstr common cmt 83d1 str1 str0 83d2 cmcsr0 ch0 83d3 cmf cmie cks1 cks0 83d4 cmcnt0 83d5 83d6 cmcor0 83d7 83d8 cmcsr1 ch1 83d9 cmf cmie cks1 cks0 83da cmcnt1 83db 83dc cmcor1 83dd 284 table a.1 on-chip supporting module registers (cont) address register bit names h'ffffxxxx abbr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module 8420 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d 8421 addral ad1 ad0 8422 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 8423 addrbl ad1 ad0 8424 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 8425 addrcl ad1 ad0 8426 addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 8427 addrdl ad1 ad0 8428 adcsr adf adie adst scan cks ch2 ch1 ch0 8429 adcr trge 8610 t1csr ovf tme cks2 cks1 cks0 tim1 8610 t1cnt (wr) 8611 t1cnt (rd) 8622 bcr2 iw31 iw30 iw21 iw20 iw11 iw10 iw01 iw00 bsc 8623 cw3 cw2 cw1 cw0 sw3 sw2 sw1 sw0 8624 wcr1 w31 w30 w21 w20 8625 w11 w10 w01 w00 862c t2csr tim2 862d cmf cmie cks2 cks1 cks0 862e t2cnt 862f 8630 t2cor 8631 285 appendix b pin states b.1 pin states table b.1 pin states during reset, and power-down pin modes pin function reset power-down class pin name power-on sleep clock ck o o system control res ii interrupt nmi i i irq0 irq7 zi address bus a1?21 o o data bus d0?15 z i/o bus control wait zi rd hh cs0 , cs1 hh cs2 , cs3 zh wrh , wrl hh mtu tioc0a, tioc0c, tioc1a, tioc1b, tioc2a, tioc2b z i/o sci txd z o rxd z i a/d converter an0?n6 z i i/o port pa18, pa19 z k pe0, pe2, pe4?e7, pe12?e14 legend: i: input o: output h: high-level output l: low-level output z: high impedance k: input pin with high impedance, output pin mode maintained. 286 b.2 bus related signal pin states table b.2 bus related signal pin states on-chip supporting module external normal space internal 16-bit space 16-bit space pin name ram space 8-bit space upper byte lower byte word/ longword upper byte lower byte word/ longword cs0 cs3 h h h h h valid valid valid rd rhh hhh l l l whh hhh hhh wrh rhh hhh hhh whh hhh l l l wrl rhh hhh hhh whh hhh hl l a21?1 address address address address address address address address d15?8 z z z z z data z data d7?0 z z z z z z data data legend: r: read w: write h: high-level output l: low-level output valid: chip select signal corresponding with accessed area is low; chip select signal in other cases is high. 287 appendix c package dimensions package dimensions of the SH7011 (tfp-100b) are shown in figure c.1. unit: mm *dimension including the plating thickness base material dimension 16.0 0.2 14 0.08 0.10 0.5 0.1 16.0 0.2 0.5 0.10 0.10 1.20 max *0.17 0.05 0 e 8 75 51 125 76 100 26 50 m *0.22 0.05 1.0 1.00 1.0 0.20 0.04 0.15 0.04 figure c.1 package dimensions (tfp-100b) SH7011 hardware manual publication date: 1st edition, december 1998 published by: electronic devices sales & marketing group semiconductor & integrated circuits group hitachi, ltd. edited by: technical documentation group ul media co., ltd. copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. |
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